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rt-thread-official/bsp/cvitek/drivers/drv_pinmux.h

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bsp: cvitek: new design for pinmux In the new design, we require the user to manually enter the PinName (as a string) in menuconfig instead of being given menu items to select. The original method will lead to too many menu item-related macros being defined in the code, causing ifdef and other codes scatter everywhere in the driver code, which is inconvenient to maintain. The new design adds a pinmux driver module to manage the multiplexing of pins. This patch provides this driver module. P.S., the reason why users are allowed to specify pinname in a string instead of the pin number is mainly because the technical manual provided by the SOC manufacturer does not have numbers for some pins, only names. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Reviewed-by: Yuanjie He <943313837@qq.com> Reviewed-by: Shell <smokewood@qq.com>
2024-05-28 16:24:47 +08:00
/*
* Copyright (c) 2006-2024, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2024/05/24 unicornx first version
*/
#ifndef __DRV_PINMUX_H__
#define __DRV_PINMUX_H__
/**
* @brief Function Selection Type
*
* FIXME: At present, we only define the ones we will use,
* not all of them. We will need to add them later.
*/
typedef enum _fs_type
{
fs_none = 0,
AUX0,
AUX1,
AUX2,
CAM_HS0,
CAM_MCLK0,
CAM_MCLK1,
CAM_VS0,
CLK25M,
CLK32K,
DBG_0,
DBG_1,
DBG_2,
DBG_3,
DBG_4,
DBG_5,
DBG_6,
DBG_7,
DBG_8,
DBG_9,
DBG_10,
DBG_11,
DBG_12,
DBG_13,
DBG_14,
DBG_15,
DBG_16,
DBG_18,
DBG_19,
EMMC_CLK,
EMMC_CMD,
EMMC_DAT_0,
EMMC_DAT_1,
EMMC_DAT_2,
EMMC_DAT_3,
EMMC_RSTN,
EPHY_LNK_LED,
EPHY_SPD_LED,
IIC0_SCL,
IIC0_SDA,
IIC1_SCL,
IIC1_SDA,
IIC2_SCL,
IIC2_SDA,
IIC3_SCL,
IIC3_SDA,
IIC4_SCL,
IIC4_SDA,
IIS1_BCLK,
IIS1_DI,
IIS1_DO,
IIS1_LRCK,
IIS1_MCLK,
IIS2_BCLK,
IIS2_DI,
IIS2_DO,
IIS2_LRCK,
IIS2_MCLK,
JTAG_TCK,
JTAG_TDI,
JTAG_TDO,
JTAG_TMS,
JTAG_CPU_TCK,
JTAG_CPU_TMS,
JTAG_CPU_TRST,
KEY_COL0,
KEY_COL1,
KEY_COL2,
KEY_COL3,
KEY_ROW0,
KEY_ROW1,
KEY_ROW2,
KEY_ROW3,
MUX_SPI1_CS,
MUX_SPI1_MISO,
MUX_SPI1_MOSI,
MUX_SPI1_SCK,
PKG_TYPE0,
PKG_TYPE1,
PKG_TYPE2,
PWM_0,
PWM_1,
PWM_2,
PWM_3,
PWM_4,
PWM_5,
PWM_6,
PWM_7,
PWM_8,
PWM_9,
PWM_10,
PWM_11,
PWM_12,
PWM_13,
PWM_14,
PWM_15,
PWR_BUTTON1,
PWR_GPIO_0,
PWR_GPIO_1,
PWR_GPIO_2,
PWR_GPIO_3,
PWR_GPIO_4,
PWR_GPIO_5,
PWR_GPIO_6,
PWR_GPIO_7,
PWR_GPIO_8,
PWR_GPIO_9,
PWR_GPIO_10,
PWR_GPIO_11,
PWR_GPIO_12,
PWR_GPIO_13,
PWR_GPIO_14,
PWR_GPIO_15,
PWR_GPIO_16,
PWR_GPIO_17,
PWR_GPIO_18,
PWR_GPIO_19,
PWR_GPIO_20,
PWR_GPIO_21,
PWR_GPIO_22,
PWR_GPIO_23,
PWR_GPIO_24,
PWR_GPIO_25,
PWR_GPIO_26,
PWR_IIC_SCL,
PWR_IIC_SDA,
PWR_IR0,
PWR_IR1,
PWR_MCU_JTAG_TCK,
PWR_MCU_JTAG_TDI,
PWR_MCU_JTAG_TDO,
PWR_MCU_JTAG_TMS,
PWR_ON,
PWR_PTEST,
PWR_RSTN,
PWR_SD1_CLK_VO37,
PWR_SD1_CMD_VO36,
PWR_SD1_D0_VO35,
PWR_SD1_D1_VO34,
PWR_SD1_D2_VO33,
PWR_SD1_D3_VO32,
PWR_SD1_CLK,
PWR_SD1_CMD,
PWR_SD1_D0,
PWR_SD1_D1,
PWR_SD1_D2,
PWR_SD1_D3,
PWR_SECTICK,
PWR_SEQ1,
PWR_SEQ2,
PWR_SEQ3,
PWR_SPINOR1_CS_X,
PWR_SPINOR1_HOLD_X,
PWR_SPINOR1_MISO,
PWR_SPINOR1_MOSI,
PWR_SPINOR1_SCK,
PWR_SPINOR1_WP_X,
PWR_UART0_RX,
PWR_UART0_TX,
PWR_UART1_RX,
PWR_UART1_TX,
PWR_VBAT_DET,
PWR_WAKEUP0,
PWR_WAKEUP1,
PWR_XTAL_CLKIN,
RMII0_IRQ,
RMII0_MDC,
RMII0_MDIO,
RMII0_REFCLKI,
RMII0_RXD0,
RMII0_RXD1,
RMII0_RXDV,
RMII0_TXCLK,
RMII0_TXD0,
RMII0_TXD1,
RMII0_TXEN,
RSTN,
SD1_CLK,
SD1_CMD,
SD1_D0,
SD1_D1,
SD1_D2,
SD1_D3,
SDIO0_CD,
SDIO0_CLK,
SDIO0_CMD,
SDIO0_D_0,
SDIO0_D_1,
SDIO0_D_2,
SDIO0_D_3,
SDIO0_PWR_EN,
SPI0_CS_X,
SPI0_SCK,
SPI0_SDI,
SPI0_SDO,
SPI1_CS_X,
SPI1_SCK,
SPI1_SDI,
SPI1_SDO,
SPI2_CS_X,
SPI2_SCK,
SPI2_SDI,
SPI2_SDO,
SPI3_CS_X,
SPI3_SCK,
SPI3_SDI,
SPI3_SDO,
SPINAND_CLK,
SPINAND_CS,
SPINAND_HOLD,
SPINAND_MISO,
SPINAND_MOSI,
SPINAND_WP,
SPINOR_CS_X,
SPINOR_HOLD_X,
SPINOR_MISO,
SPINOR_MOSI,
SPINOR_SCK,
SPINOR_WP_X,
UART0_RX,
UART0_TX,
UART1_CTS,
UART1_RTS,
UART1_RX,
UART1_TX,
UART2_CTS,
UART2_RTS,
UART2_RX,
UART2_TX,
UART3_CTS,
UART3_RTS,
UART3_RX,
UART3_TX,
UART4_CTS,
UART4_RTS,
UART4_RX,
UART4_TX,
USB_ID,
USB_VBUS_DET,
USB_VBUS_EN,
VI0_CLK,
VI0_D_0,
VI0_D_1,
VI0_D_2,
VI0_D_3,
VI0_D_4,
VI0_D_5,
VI0_D_6,
VI0_D_7,
VI0_D_8,
VI0_D_9,
VI0_D_10,
VI0_D_11,
VI0_D_12,
VI0_D_13,
VI0_D_14,
VI0_D_15,
VI1_CLK,
VI1_D_0,
VI1_D_1,
VI1_D_2,
VI1_D_3,
VI1_D_4,
VI1_D_5,
VI1_D_6,
VI1_D_7,
VI1_D_8,
VI1_D_9,
VI1_D_10,
VI1_D_11,
VI1_D_12,
VI1_D_13,
VI1_D_14,
VI1_D_15,
VI1_D_16,
VI1_D_17,
VI1_D_18,
VI2_CLK,
VI2_D_0,
VI2_D_1,
VI2_D_2,
VI2_D_3,
VI2_D_4,
VI2_D_5,
VI2_D_6,
VI2_D_7,
VO_CLK0,
VO_CLK1,
VO_D_0,
VO_D_1,
VO_D_2,
VO_D_3,
VO_D_4,
VO_D_5,
VO_D_6,
VO_D_7,
VO_D_8,
VO_D_9,
VO_D_10,
VO_D_11,
VO_D_12,
VO_D_13,
VO_D_14,
VO_D_15,
VO_D_16,
VO_D_17,
VO_D_18,
VO_D_19,
VO_D_20,
VO_D_21,
VO_D_22,
VO_D_23,
VO_D_24,
VO_D_25,
VO_D_26,
VO_D_27,
VO_D_28,
VO_D_29,
VO_D_30,
VO_D_31,
WG0_D0,
WG0_D1,
WG1_D0,
WG1_D1,
WG2_D0,
WG2_D1,
XGPIOA_0,
XGPIOA_1,
XGPIOA_2,
XGPIOA_3,
XGPIOA_4,
XGPIOA_5,
XGPIOA_6,
XGPIOA_7,
XGPIOA_8,
XGPIOA_9,
XGPIOA_10,
XGPIOA_11,
XGPIOA_12,
XGPIOA_13,
XGPIOA_14,
XGPIOA_15,
XGPIOA_16,
XGPIOA_17,
XGPIOA_18,
XGPIOA_19,
XGPIOA_20,
XGPIOA_21,
XGPIOA_22,
XGPIOA_23,
XGPIOA_24,
XGPIOA_25,
XGPIOA_26,
XGPIOA_27,
XGPIOA_28,
XGPIOA_29,
XGPIOA_30,
XGPIOB_0,
XGPIOB_1,
XGPIOB_2,
XGPIOB_3,
XGPIOB_4,
XGPIOB_5,
XGPIOB_6,
XGPIOB_7,
XGPIOB_8,
XGPIOB_9,
XGPIOB_10,
XGPIOB_11,
XGPIOB_12,
XGPIOB_13,
XGPIOB_14,
XGPIOB_15,
XGPIOB_16,
XGPIOB_17,
XGPIOB_18,
XGPIOB_19,
XGPIOB_20,
XGPIOB_21,
XGPIOB_22,
XGPIOB_23,
XGPIOB_24,
XGPIOB_25,
XGPIOB_26,
XGPIOB_27,
XGPIOC_0,
XGPIOC_1,
XGPIOC_2,
XGPIOC_3,
XGPIOC_4,
XGPIOC_5,
XGPIOC_6,
XGPIOC_7,
XGPIOC_8,
XGPIOC_9,
XGPIOC_10,
XGPIOC_11,
XGPIOC_12,
XGPIOC_13,
XGPIOC_14,
XGPIOC_15,
XGPIOC_16,
XGPIOC_17,
XGPIOC_18,
XGPIOC_19,
XGPIOC_20,
XGPIOC_21,
XGPIOC_22,
XGPIOC_23,
XGPIOC_24,
XGPIOC_25,
} fs_type;
/**
* @brief configure pin multiplex
*
* @param pin_name pin name string
* @param func_type function type enum
* @param whitelist pin name whilelist which is allowed to set. Ignore check
* if NULL.
* NOTE: whitelist should be a string list ended with NULL.
*
* @return RT_EOK if succeeded
* else: something wrong occurred and config is abandoned.
*/
extern int pinmux_config(const char *pin_name, fs_type func_type, const char *whitelist[]);
#endif