297 lines
15 KiB
C
297 lines
15 KiB
C
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/**************************************************************************//**
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* @file pwm.h
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* @version V1.00
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* $Revision: 22 $
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* $Date: 15/11/16 2:08p $
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* @brief NUC472/NUC442 PWM driver header file
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*
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* @note
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* Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
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*****************************************************************************/
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#ifndef __PWM_H__
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#define __PWM_H__
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
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@{
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*/
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/** @addtogroup NUC472_442_PWM_Driver PWM Driver
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@{
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*/
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/** @addtogroup NUC472_442_PWM_EXPORTED_CONSTANTS PWM Exported Constants
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@{
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*/
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#define PWM_CHANNEL_NUM (6) /*!< PWM channel number \hideinitializer */
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#define PWM_CH0 (0UL) /*!< PWM channel 0 \hideinitializer */
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#define PWM_CH1 (1UL) /*!< PWM channel 1 \hideinitializer */
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#define PWM_CH2 (2UL) /*!< PWM channel 2 \hideinitializer */
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#define PWM_CH3 (3UL) /*!< PWM channel 3 \hideinitializer */
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#define PWM_CH4 (4UL) /*!< PWM channel 4 \hideinitializer */
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#define PWM_CH5 (5UL) /*!< PWM channel 5 \hideinitializer */
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#define PWM_CH_0_MASK (1UL) /*!< PWM channel 0 mask \hideinitializer */
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#define PWM_CH_1_MASK (2UL) /*!< PWM channel 1 mask \hideinitializer */
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#define PWM_CH_2_MASK (4UL) /*!< PWM channel 2 mask \hideinitializer */
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#define PWM_CH_3_MASK (8UL) /*!< PWM channel 3 mask \hideinitializer */
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#define PWM_CH_4_MASK (16UL) /*!< PWM channel 4 mask \hideinitializer */
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#define PWM_CH_5_MASK (32UL) /*!< PWM channel 5 mask \hideinitializer */
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#define PWM_CLK_DIV_1 (4UL) /*!< PWM clock divide by 1 \hideinitializer */
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#define PWM_CLK_DIV_2 (0UL) /*!< PWM clock divide by 2 \hideinitializer */
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#define PWM_CLK_DIV_4 (1UL) /*!< PWM clock divide by 4 \hideinitializer */
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#define PWM_CLK_DIV_8 (2UL) /*!< PWM clock divide by 8 \hideinitializer */
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#define PWM_CLK_DIV_16 (3UL) /*!< PWM clock divide by 16 \hideinitializer */
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#define PWM_EDGE_ALIGNED (0UL) /*!< PWM working in edge aligned type \hideinitializer */
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#define PWM_CENTER_ALIGNED (1UL) /*!< PWM working in center aligned type \hideinitializer */
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#define PWM_TRIGGER_ADC_RISING_EDGE_POINT (0x1000000UL) /*!< PWM trigger ADC while output rising edge is detected \hideinitializer */
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#define PWM_TRIGGER_ADC_FALLING_EDGE_POINT (0x10000UL) /*!< PWM trigger ADC while output falling edge is detected \hideinitializer */
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#define PWM_TRIGGER_ADC_CENTER_POINT (0x100UL) /*!< PWM trigger ADC while counter matches (CNR + 1) \hideinitializer */
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#define PWM_TRIGGER_ADC_PERIOD_POINT (0x1UL) /*!< PWM trigger ADC while counter down count to 0 \hideinitializer */
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#define PWM_BRK0_BKP0 (PWM_BRKCTL_BRK0EN_Msk) /*!< Brake0 signal source from external pin BKP0 \hideinitializer */
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#define PWM_BRK0_CPO0 (PWM_BRKCTL_CPO0BKEN_Msk) /*!< Brake0 signal source from analog comparator 0 output \hideinitializer */
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#define PWM_BRK0_CPO1 (PWM_BRKCTL_CPO1BKEN_Msk) /*!< Brake0 signal source from analog comparator 1 output \hideinitializer */
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#define PWM_BRK0_CPO2 (PWM_BRKCTL_CPO2BKEN_Msk) /*!< Brake0 signal source from analog comparator 2 output \hideinitializer */
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#define PWM_BRK1_LVDBK (PWM_BRKCTL_LVDBKEN_Msk) /*!< Brake1 signal source from level detect \hideinitializer */
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#define PWM_BK1SEL_BKP1 (0UL << PWM_BRKCTL_BK1SEL_Pos) /*!< Brake1 signal source from external pin BKP1 \hideinitializer */
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#define PWM_BK1SEL_CPO0 (1UL << PWM_BRKCTL_BK1SEL_Pos) /*!< Brake1 signal source from analog comparator 0 output \hideinitializer */
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#define PWM_BK1SEL_CPO1 (2UL << PWM_BRKCTL_BK1SEL_Pos) /*!< Brake1 signal source from analog comparator 1 output \hideinitializer */
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#define PWM_PERIOD_INT_UNDERFLOW (0) /*!< PWM period interrupt trigger if counter underflow \hideinitializer */
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#define PWM_PERIOD_INT_MATCH_CNR (1UL) /*!< PWM period interrupt trigger if counter match CNR \hideinitializer */
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#define PWM_DUTY_INT_MATCH_CMR_DN (0) /*!< PWM duty interrupt if counter match CNR during down counting \hideinitializer */
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#define PWM_DUTY_INT_MATCH_CMR_UP (0x100UL) /*!< PWM duty interrupt if counter match CNR during up counting \hideinitializer */
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#define PWM_FALLING_LATCH_INT_ENABLE (0x1000000UL) /*!< PWM falling latch interrupt enable \hideinitializer */
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#define PWM_RISING_LATCH_INT_ENABLE (0x10000UL) /*!< PWM rising latch interrupt enable \hideinitializer */
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#define PWM_RISING_FALLING_LATCH_INT_ENABLE (0x1010000UL) /*!< PWM rising latch interrupt enable \hideinitializer */
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#define PWM_FALLING_LATCH_INT_FLAG (PWM_FALLING_LATCH_INT_ENABLE) /*!< PWM falling latch condition happened \hideinitializer */
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#define PWM_RISING_LATCH_INT_FLAG (PWM_RISING_LATCH_INT_ENABLE) /*!< PWM rising latch condition happened \hideinitializer */
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#define PWM_RISING_FALLING_LATCH_INT_FLAG (PWM_RISING_FALLING_LATCH_INT_ENABLE) /*!< PWM rising latch condition happened \hideinitializer */
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/*@}*/ /* end of group NUC472_442_PWM_EXPORTED_CONSTANTS */
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/** @addtogroup NUC472_442_PWM_EXPORTED_FUNCTIONS PWM Exported Functions
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@{
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*/
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/**
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* @brief This macro enable complementary mode
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* @param[in] pwm The base address of PWM module
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* @return None
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* \hideinitializer
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*/
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#define PWM_ENABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL = (pwm)->CTL | PWM_CTL_OUTMODE_Msk)
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/**
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* @brief This macro disable complementary mode, and enable independent mode.
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* @param[in] pwm The base address of PWM module
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* @return None
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* \hideinitializer
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*/
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#define PWM_DISABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL = (pwm)->CTL & ~PWM_CTL_OUTMODE_Msk)
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/**
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* @brief This macro enable group mode
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* @param[in] pwm The base address of PWM module
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* @return None
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* \hideinitializer
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*/
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#define PWM_ENABLE_GROUP_MODE(pwm) ((pwm)->CTL = (pwm)->CTL | PWM_CTL_GROUPEN_Msk)
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/**
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* @brief This macro disable group mode
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* @param[in] pwm The base address of PWM module
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* @return None
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* \hideinitializer
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*/
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#define PWM_DISABLE_GROUP_MODE(pwm) ((pwm)->CTL = (pwm)->CTL & ~PWM_CTL_GROUPEN_Msk)
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/**
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* @brief This macro enable synchronous mode
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* @param[in] pwm The base address of PWM module
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* @return None
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* \hideinitializer
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*/
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#define PWM_ENABLE_SYNC_MODE(pwm) ((pwm)->CTL = (pwm)->CTL | PWM_CTL_SYNCEN_Msk)
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/**
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* @brief This macro disable synchronous mode, and enable independent mode.
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* @param[in] pwm The base address of PWM module
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* @return None
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* \hideinitializer
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*/
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#define PWM_DISABLE_SYNC_MODE(pwm) ((pwm)->CTL = (pwm)->CTL & ~PWM_CTL_SYNCEN_Msk)
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/**
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* @brief This macro enable output inverter of specified channel(s)
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
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* Bit 0 represents channel 0, bit 1 represents channel 1...
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* @return None
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* \hideinitializer
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*/
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#define PWM_ENABLE_OUTPUT_INVERTER(pwm, u32ChannelMask) ((pwm)->CTL = (((pwm)->CTL & ~PWM_CTL_PINV_Msk) | ((u32ChannelMask) << PWM_CTL_PINV_Pos)))
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/**
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* @brief This macro get captured rising data
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
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* @return None
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* \hideinitializer
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*/
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#define PWM_GET_CAPTURE_RISING_DATA(pwm, u32ChannelNum) (*(__IO uint32_t *) (&(pwm)->RCAPDAT0 + 2 * (u32ChannelNum)))
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/**
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* @brief This macro get captured falling data
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
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* @return None
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* \hideinitializer
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*/
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#define PWM_GET_CAPTURE_FALLING_DATA(pwm, u32ChannelNum) (*(__IO uint32_t *) (&(pwm)->FCAPDAT0 + 2 * (u32ChannelNum)))
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/**
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* @brief This macro mask output output logic to high or low
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
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* Bit 0 represents channel 0, bit 1 represents channel 1...
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* @param[in] u32LevelMask Output logic to high or low
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* @return None
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* \hideinitializer
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*/
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#define PWM_MASK_OUTPUT(pwm, u32ChannelMask, u32LevelMask) ((pwm)->MSKEN |= (u32ChannelMask))
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/**
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* @brief This macro set the prescaler of the selected channel
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
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* @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 1 ~ 0xFF
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* @return None
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* @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed,
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* channel 1 will also be affected.
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* \hideinitializer
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*/
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#define PWM_SET_PRESCALER(pwm, u32ChannelNum, u32Prescaler) \
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(pwm->CLKPSC = ((pwm)->CLKPSC & ~(PWM_CLKPSC_CLKPSC01_Msk << (((u32ChannelNum) >> 1) * 8))) | ((u32Prescaler) << (((u32ChannelNum) >> 1) * 8)))
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/**
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* @brief This macro set the divider of the selected channel
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
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* @param[in] u32Divider Clock divider of specified channel. Valid values are
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* - \ref PWM_CLK_DIV_1
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* - \ref PWM_CLK_DIV_2
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* - \ref PWM_CLK_DIV_4
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* - \ref PWM_CLK_DIV_8
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* - \ref PWM_CLK_DIV_16
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* @return None
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* \hideinitializer
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*/
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#define PWM_SET_DIVIDER(pwm, u32ChannelNum, u32Divider) \
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((pwm)->CLKDIV = ((pwm)->CLKDIV & ~(PWM_CLKDIV_CLKDIV0_Msk << ((u32ChannelNum) * 4))) | ((u32Divider) << ((u32ChannelNum) * 4)))
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/**
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* @brief This macro set the duty of the selected channel
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
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* @param[in] u32CMR Duty of specified channel. Valid values are between 0~0xFFFF
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* @return None
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* @note This new setting will take effect on next PWM period
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* \hideinitializer
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*/
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#define PWM_SET_CMR(pwm, u32ChannelNum, u32CMR) ((pwm)->CMPDAT[(u32ChannelNum)] = (u32CMR))
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/**
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* @brief This macro set the period of the selected channel
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
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* @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF
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* @return None
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* @note This new setting will take effect on next PWM period
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* @note PWM counter will stop if period length set to 0
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* \hideinitializer
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*/
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#define PWM_SET_CNR(pwm, u32ChannelNum, u32CNR) ((pwm)->PERIOD[(u32ChannelNum)] = (u32CNR))
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/**
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* @brief This macro set the PWM aligned type
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
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* Bit 0 represents channel 0, bit 1 represents channel 1...
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* @param[in] u32AlignedType PWM aligned type, valid values are:
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* - \ref PWM_EDGE_ALIGNED
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* - \ref PWM_CENTER_ALIGNED
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* @return None
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* \hideinitializer
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*/
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#define PWM_SET_ALIGNED_TYPE(pwm, u32ChannelMask, u32AlignedType) \
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do { \
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(pwm)->CTL = ((pwm)->CTL & ~PWM_CTL_CNTTYPE_Msk); \
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if ((u32AlignedType) == PWM_CENTER_ALIGNED) \
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(pwm)->CTL = ((pwm)->CTL | ((u32ChannelMask) << PWM_CTL_CNTTYPE_Pos)); \
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} while(0)
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uint32_t PWM_ConfigOutputChannel(PWM_T *pwm,
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uint32_t u32ChannelNum,
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uint32_t u32Frequency,
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uint32_t u32DutyCycle);
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uint32_t PWM_ConfigCaptureChannel (PWM_T *pwm,
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uint32_t u32ChannelNum,
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uint32_t u32UnitTimeNsec,
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uint32_t u32CaptureEdge);
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void PWM_Start(PWM_T *pwm, uint32_t u32ChannelMask);
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void PWM_Stop(PWM_T *pwm, uint32_t u32ChannelMask);
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void PWM_ForceStop(PWM_T *pwm, uint32_t u32ChannelMask);
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void PWM_EnableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
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void PWM_DisableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum);
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void PWM_ClearADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
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uint32_t PWM_GetADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum);
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void PWM_EnableFaultBrake(PWM_T *pwm,
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uint32_t u32ChannelMask,
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uint32_t u32LevelMask,
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uint32_t u32BrakeSource);
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void PWM_ClearFaultBrakeFlag(PWM_T *pwm, uint32_t u32BrakeSource);
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void PWM_EnableCapture(PWM_T *pwm, uint32_t u32ChannelMask);
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void PWM_DisableCapture(PWM_T *pwm, uint32_t u32ChannelMask);
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void PWM_EnableOutput(PWM_T *pwm, uint32_t u32ChannelMask);
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void PWM_DisableOutput(PWM_T *pwm, uint32_t u32ChannelMask);
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void PWM_EnableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Duration);
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void PWM_DisableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum);
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void PWM_EnableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge);
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void PWM_DisableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge);
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void PWM_ClearCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge);
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uint32_t PWM_GetCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
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void PWM_EnableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType);
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void PWM_DisableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum);
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void PWM_ClearDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
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uint32_t PWM_GetDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
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void PWM_EnableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource);
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void PWM_DisableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource);
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void PWM_ClearFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource);
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uint32_t PWM_GetFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource);
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void PWM_EnablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType);
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void PWM_DisablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum);
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void PWM_ClearPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
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uint32_t PWM_GetPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
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/*@}*/ /* end of group NUC472_442_PWM_EXPORTED_FUNCTIONS */
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/*@}*/ /* end of group NUC472_442_PWM_Driver */
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/*@}*/ /* end of group NUC472_442_Device_Driver */
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#ifdef __cplusplus
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}
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#endif
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#endif //__PWM_H__
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/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
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