234 lines
6.8 KiB
C
234 lines
6.8 KiB
C
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/*
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* File : board.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2015, RT-Thread Development Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Change Logs:
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* Date Author Notes
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* 2009-01-05 Bernard first implementation
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* 2017-08-25 LongfeiMa transplantation for stm32h7xx
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*/
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#include <rtthread.h>
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#include "board.h"
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#include "sram.h"
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#include "drv_mpu.h"
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#include "drv_led.h"
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#include "drv_usart.h"
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/**
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* @addtogroup STM32
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*/
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/**
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* @brief System Clock Configuration
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* The system Clock is configured as follow :
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* System Clock source = PLL (HSE BYPASS)
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* SYSCLK(Hz) = 400000000 (CPU Clock)
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* HCLK(Hz) = 200000000 (AXI and AHBs Clock)
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* AHB Prescaler = 2
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* D1 APB3 Prescaler = 2 (APB3 Clock 100MHz)
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* D2 APB1 Prescaler = 2 (APB1 Clock 100MHz)
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* D2 APB2 Prescaler = 2 (APB2 Clock 100MHz)
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* D3 APB4 Prescaler = 2 (APB4 Clock 100MHz)
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* HSE Frequency(Hz) = 8000000
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* PLL_M = 4
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* PLL_N = 400
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* PLL_P = 2
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* PLL_Q = 4
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* PLL_R = 2
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* VDD(V) = 3.3
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* Flash Latency(WS) = 4
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* @param None
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* @retval None
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*/
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static void SystemClock_Config(void)
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{
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RCC_ClkInitTypeDef RCC_ClkInitStruct;
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RCC_OscInitTypeDef RCC_OscInitStruct;
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HAL_StatusTypeDef ret = HAL_OK;
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/*!< Supply configuration update enable */
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MODIFY_REG(PWR->CR3, PWR_CR3_SCUEN, 0);
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/* The voltage scaling allows optimizing the power consumption when the device is
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clocked below the maximum system frequency, to update the voltage scaling value
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regarding system frequency refer to product datasheet. */
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__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
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while ((PWR->D3CR & (PWR_D3CR_VOSRDY)) != PWR_D3CR_VOSRDY) {}
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/* Enable D2 domain SRAM3 Clock (0x30040000 AXI)*/
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__HAL_RCC_D2SRAM3_CLK_ENABLE();
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/* Enable HSE Oscillator and activate PLL with HSE as source */
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
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RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
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RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
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RCC_OscInitStruct.CSIState = RCC_CSI_OFF;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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RCC_OscInitStruct.PLL.PLLM = 4;
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RCC_OscInitStruct.PLL.PLLN = 400;
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RCC_OscInitStruct.PLL.PLLP = 2;
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RCC_OscInitStruct.PLL.PLLR = 2;
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RCC_OscInitStruct.PLL.PLLQ = 4;
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RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
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RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
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ret = HAL_RCC_OscConfig(&RCC_OscInitStruct);
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if(ret != HAL_OK)
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{
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while (1) { ; }
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}
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/* Select PLL as system clock source and configure bus clocks dividers */
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RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 | \
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RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1);
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
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RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
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RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
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ret = HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
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if(ret != HAL_OK)
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{
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while (1) { ; }
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}
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/*activate CSI clock mondatory for I/O Compensation Cell*/
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__HAL_RCC_CSI_ENABLE() ;
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/* Enable SYSCFG clock mondatory for I/O Compensation Cell */
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__HAL_RCC_SYSCFG_CLK_ENABLE() ;
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/* Enables the I/O Compensation Cell */
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HAL_EnableCompensationCell();
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}
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/**
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* @brief CPU L1-Cache enable.
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* @param None
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* @retval None
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*/
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static void CPU_CACHE_Enable(void)
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{
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// /* Enable branch prediction */
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// SCB->CCR |= (1 << 18);
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// __DSB();
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/* Enable I-Cache */
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SCB_EnableICache();
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/* Enable D-Cache */
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SCB_EnableDCache();
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}
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/**
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* This is the timer interrupt service routine.
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*
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*/
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void SysTick_Handler(void)
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{
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/* enter interrupt */
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rt_interrupt_enter();
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/* tick for HAL Library */
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HAL_IncTick();
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rt_tick_increase();
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/* leave interrupt */
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rt_interrupt_leave();
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}
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/* re-implementat tick interface for STM32 HAL */
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HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
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{
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/*Configure the SysTick to have interrupt in 1ms time basis*/
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HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/RT_TICK_PER_SECOND);
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/*Configure the SysTick IRQ priority */
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HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0);
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/* Return function status */
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return HAL_OK;
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}
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void HAL_Delay(__IO uint32_t Delay)
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{
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rt_thread_delay(Delay);
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}
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void HAL_SuspendTick(void)
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{
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/* we should not suspend tick */
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}
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void HAL_ResumeTick(void)
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{
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/* we should not resume tick */
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}
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/**
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* This function will initial STM32 board.
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*/
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void rt_hw_board_init()
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{
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/* Configure the MPU attributes as Write Through */
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mpu_init();
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/* Enable the CPU Cache */
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CPU_CACHE_Enable();
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/* STM32F7xx HAL library initialization:
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- Configure the Flash ART accelerator on ITCM interface
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- Configure the Systick to generate an interrupt each 1 msec
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- Set NVIC Group Priority to 4
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- Global MSP (MCU Support Package) initialization
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*/
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HAL_Init();
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/* Configure the system clock @ 200 Mhz */
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SystemClock_Config();
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/* init systick */
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SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
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/* set pend exception priority */
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NVIC_SetPriority(PendSV_IRQn, (1 << __NVIC_PRIO_BITS) - 1);
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#ifdef RT_USING_COMPONENTS_INIT
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rt_components_board_init();
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#endif
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#ifdef RT_USING_EXT_SDRAM
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rt_system_heap_init((void*)EXT_SDRAM_BEGIN, (void*)EXT_SDRAM_END);
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sram_init();
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#else
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rt_system_heap_init((void*)HEAP_BEGIN, (void*)HEAP_END);
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#endif
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#ifdef RT_USING_CONSOLE
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rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
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#endif
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}
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/*@}*/
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