515 lines
16 KiB
C
515 lines
16 KiB
C
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/**
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* @file spimss.c
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* @brief This file contains the function implementations for the
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* Serial Peripheral Interface (SPIMSS) peripheral module.
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*/
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/* *****************************************************************************
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* Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
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* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Except as contained in this notice, the name of Maxim Integrated
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* Products, Inc. shall not be used except as stated in the Maxim Integrated
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* Products, Inc. Branding Policy.
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*
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* The mere transfer of this software does not imply any licenses
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* of trade secrets, proprietary technology, copyrights, patents,
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* trademarks, maskwork rights, or any other form of intellectual
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* property whatsoever. Maxim Integrated Products, Inc. retains all
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* ownership rights.
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*
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* $Date: 2019-05-06 14:44:04 -0500 (Mon, 06 May 2019) $
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* $Revision: 43157 $
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*
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**************************************************************************** */
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/* **** Includes **** */
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#include <string.h>
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#include <stdio.h>
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#include <stdint.h>
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#include "mxc_config.h"
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#include "mxc_assert.h"
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#include "mxc_sys.h"
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#include "spimss.h"
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#include "mxc_lock.h"
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/**
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* @ingroup spimss
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* @{
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*/
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/* **** Definitions **** */
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/* **** Globals **** */
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typedef struct {
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spimss_req_t *req;
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} spimss_req_state_t;
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static spimss_req_state_t states[MXC_SPIMSS_INSTANCES];
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/* **** Functions **** */
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static int SPIMSS_TransSetup(mxc_spimss_regs_t *spi, spimss_req_t *req, int master);
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static uint32_t SPIMSS_MasterTransHandler(mxc_spimss_regs_t *spi, spimss_req_t *req);
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static uint32_t SPIMSS_TransHandler(mxc_spimss_regs_t *spi, spimss_req_t *req);
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static uint32_t SPIMSS_SlaveTransHandler(mxc_spimss_regs_t *spi, spimss_req_t *req);
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/* ************************************************************************** */
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int SPIMSS_Init(mxc_spimss_regs_t *spi, unsigned mode, unsigned freq, const sys_cfg_spimss_t* sys_cfg)
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{
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int spi_num, error;
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unsigned int spimss_clk;
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unsigned int pol, pha; // Polarity and phase of the clock (SPI mode)
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spi_num = MXC_SPIMSS_GET_IDX(spi);
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MXC_ASSERT(spi_num >= 0);
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if (mode > 3) {
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return E_BAD_PARAM;
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}
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if ((error = SYS_SPIMSS_Init(spi, sys_cfg)) != E_NO_ERROR) {
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return error;
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}
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states[spi_num].req = NULL;
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spi->ctrl &= ~(MXC_F_SPIMSS_CTRL_SPIEN); // Keep the SPI Disabled (This is the SPI Start)
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// Check if frequency is too high
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if (freq > PeripheralClock) {
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return E_BAD_PARAM;
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}
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// Set the bit rate
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spimss_clk = PeripheralClock;
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spi->brg = (spimss_clk / freq) >> 1;
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// Set the mode
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pol = mode >> 1; // Get the polarity out of the mode input value
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pha = mode & 1; // Get the phase out of the mode input value
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spi->ctrl = (spi->ctrl & ~(MXC_F_SPIMSS_CTRL_CLKPOL)) | (pol << MXC_F_SPIMSS_CTRL_CLKPOL_POS); // polarity
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spi->ctrl = (spi->ctrl & ~(MXC_F_SPIMSS_CTRL_PHASE)) | (pha << MXC_F_SPIMSS_CTRL_PHASE_POS); // phase
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spi->status &= ~(MXC_F_SPIMSS_STATUS_IRQ);
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return E_NO_ERROR;
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}
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/* ************************************************************************* */
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int SPIMSS_Shutdown(mxc_spimss_regs_t *spi)
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{
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int spi_num, err;
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spimss_req_t *temp_req;
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// Disable and turn off the SPI transaction.
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spi->ctrl = 0; // Interrupts, SPI transaction all turned off
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spi->status = 0;
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spi->mod = 0;
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// Reset FIFO counters
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spi->dma &= ~(MXC_F_SPIMSS_DMA_RX_FIFO_CNT|MXC_F_SPIMSS_DMA_TX_FIFO_CNT);
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// Call all of the pending callbacks for this SPI
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spi_num = MXC_SPIMSS_GET_IDX(spi);
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if (states[spi_num].req != NULL) {
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// Save the request
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temp_req = states[spi_num].req;
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// Unlock this SPI
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mxc_free_lock((uint32_t*)&states[spi_num].req);
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// Callback if not NULL
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if (temp_req->callback != NULL) {
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temp_req->callback(temp_req, E_SHUTDOWN);
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}
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}
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spi->status = 0;
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// Clear system level configurations
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if ((err = SYS_SPIMSS_Shutdown(spi)) != E_NO_ERROR) {
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return err;
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}
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return E_NO_ERROR;
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}
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/* ************************************************************************** */
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int SPIMSS_TransSetup(mxc_spimss_regs_t *spi, spimss_req_t *req, int master)
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{
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int spi_num;
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spi->ctrl &= ~(MXC_F_SPIMSS_CTRL_SPIEN); // Make sure the Initiation
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// of SPI Start is disabled.
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spi->mod |= MXC_F_SPIMSS_MOD_TX_LJ; // Making sure data is left
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// justified.
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if ((req->tx_data == NULL) && (req->rx_data == NULL)) {
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return -1;
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}
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spi_num = MXC_SPIMSS_GET_IDX(spi);
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MXC_ASSERT(spi_num >= 0);
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if (req->len == 0) {
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return 0;
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}
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req->tx_num = 0;
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req->rx_num = 0;
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if (mxc_get_lock((uint32_t*)&states[spi_num].req, (uint32_t)req) != E_NO_ERROR) {
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return E_BUSY;
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}
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if (master) { // Enable master mode
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spi->ctrl |= MXC_F_SPIMSS_CTRL_MMEN; // SPI configured as master.
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spi->mod |= MXC_F_SPIMSS_CTRL_MMEN; // SSEL pin is an output.
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} else { // Enable slave mode
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spi->ctrl &= ~(MXC_F_SPIMSS_CTRL_MMEN); // SPI configured as slave.
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spi->mod &= ~(MXC_F_SPIMSS_CTRL_MMEN); // SSEL pin is an input.
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}
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// Setup the character size
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if (req->bits <16) {
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MXC_SETFIELD(spi->mod, MXC_F_SPIMSS_MOD_NUMBITS , req->bits << MXC_F_SPIMSS_MOD_NUMBITS_POS);
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} else {
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MXC_SETFIELD(spi->mod, MXC_F_SPIMSS_MOD_NUMBITS , 0 << MXC_F_SPIMSS_MOD_NUMBITS_POS);
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}
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// Setup the slave select
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spi->mod |= MXC_F_SPIMSS_MOD_SSV; // Assert a high on Slave Select,
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// to get the line ready for active low later
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// Clear the TX and RX FIFO
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spi->dma |= (MXC_F_SPIMSS_DMA_TX_FIFO_CLEAR | MXC_F_SPIMSS_DMA_RX_FIFO_CLEAR);
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return E_NO_ERROR;
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}
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/* ************************************************************************** */
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void SPIMSS_Handler(mxc_spimss_regs_t *spi) // From the IRQ
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{
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int spi_num;
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uint32_t flags;
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unsigned int int_enable;
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flags = spi->status;
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spi->status = flags;
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spi->status|= 0x80; // clear interrupt
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spi_num = MXC_SPIMSS_GET_IDX(spi);
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int_enable = 0;
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if (states[spi_num].req != NULL) {
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if ((spi->ctrl & MXC_F_SPIMSS_CTRL_MMEN) >> MXC_F_SPIMSS_CTRL_MMEN_POS) {
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int_enable = SPIMSS_MasterTransHandler(spi, states[spi_num].req);
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} else {
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int_enable = SPIMSS_SlaveTransHandler(spi, states[spi_num].req);
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}
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}
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if (int_enable==1) {
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spi->ctrl |= (MXC_F_SPIMSS_CTRL_IRQE );
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}
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}
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/* ************************************************************************** */
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int SPIMSS_MasterTrans(mxc_spimss_regs_t *spi, spimss_req_t *req)
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{
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int error;
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if ((error = SPIMSS_TransSetup(spi, req, 1)) != E_NO_ERROR) {
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return error;
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}
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req->callback = NULL;
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spi->mod &= ~(MXC_F_SPIMSS_MOD_SSV); // This will assert the Slave Select.
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spi->ctrl |= MXC_F_SPIMSS_CTRL_SPIEN; // Enable/Start SPI
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while (SPIMSS_MasterTransHandler(spi,req)!=0) {
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}
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spi->mod |= MXC_F_SPIMSS_MOD_SSV;
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spi->ctrl &= ~(MXC_F_SPIMSS_CTRL_SPIEN); // Last of the SPIMSS value has been transmitted...
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// stop the transmission...
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return E_NO_ERROR;
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}
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/* ************************************************************************** */
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int SPIMSS_SlaveTrans(mxc_spimss_regs_t *spi, spimss_req_t *req)
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{
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int error;
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if ((error = SPIMSS_TransSetup(spi, req,0)) != E_NO_ERROR) {
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return error;
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}
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while (SPIMSS_SlaveTransHandler(spi,req)!=0) {
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spi->ctrl |= MXC_F_SPIMSS_CTRL_SPIEN; // Enable/Start SPI
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while ((spi->status & MXC_F_SPIMSS_STATUS_TXST) == MXC_F_SPIMSS_STATUS_TXST) {}
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}
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spi->ctrl &= ~(MXC_F_SPIMSS_CTRL_SPIEN); // Last of the SPIMSS value has been transmitted...
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// stop the transmission...
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return E_NO_ERROR;
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}
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/* ************************************************************************** */
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int SPIMSS_MasterTransAsync(mxc_spimss_regs_t *spi, spimss_req_t *req)
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{
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int error;
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uint8_t int_enable;
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if ((error = SPIMSS_TransSetup(spi, req, 1) )!= E_NO_ERROR) {
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return error;
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}
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int_enable = SPIMSS_MasterTransHandler(spi,req);
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spi->mod ^= MXC_F_SPIMSS_MOD_SSV; // This will assert the Slave Select.
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spi->ctrl |= MXC_F_SPIMSS_CTRL_SPIEN; // Enable/Start SPI
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if (int_enable==1) {
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spi->ctrl |= (MXC_F_SPIMSS_CTRL_IRQE | MXC_F_SPIMSS_CTRL_STR);
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}
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return E_NO_ERROR;
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}
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/* ************************************************************************** */
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int SPIMSS_SlaveTransAsync(mxc_spimss_regs_t *spi, spimss_req_t *req)
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{
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int error;
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uint8_t int_enable;
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if ((error = SPIMSS_TransSetup(spi, req, 0)) != E_NO_ERROR) {
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return error;
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}
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int_enable = SPIMSS_SlaveTransHandler(spi,req);
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spi->ctrl |= MXC_F_SPIMSS_CTRL_SPIEN; // Enable/Start SPI
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if (int_enable==1) { // Trigger a SPI Interrupt
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spi->ctrl |= (MXC_F_SPIMSS_CTRL_IRQE );
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}
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return E_NO_ERROR;
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}
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/* ************************************************************************** */
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uint32_t SPIMSS_MasterTransHandler(mxc_spimss_regs_t *spi, spimss_req_t *req)
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{
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unsigned start_set = 0;
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uint32_t retval;
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if (!start_set) {
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start_set = 1;
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retval = SPIMSS_TransHandler(spi,req);
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}
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return retval;
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}
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/* ************************************************************************** */
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uint32_t SPIMSS_SlaveTransHandler(mxc_spimss_regs_t *spi, spimss_req_t *req)
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{
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return SPIMSS_TransHandler(spi,req);
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}
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/* ************************************************************************** */
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uint32_t SPIMSS_TransHandler(mxc_spimss_regs_t *spi, spimss_req_t *req)
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{
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unsigned tx_avail, rx_avail;
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int remain, spi_num;
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uint32_t int_en =0;
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uint32_t length =req->len;
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spi_num = MXC_SPIMSS_GET_IDX(spi);
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// Read the RX FIFO
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if (req->rx_data != NULL) {
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// Wait for there to be data in the RX FIFO
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rx_avail = ((spi->dma & MXC_F_SPIMSS_DMA_RX_FIFO_CNT) >> MXC_F_SPIMSS_DMA_RX_FIFO_CNT_POS);
|
||
|
|
if ((length - req->rx_num) < rx_avail) {
|
||
|
|
rx_avail = (length - req->rx_num);
|
||
|
|
}
|
||
|
|
|
||
|
|
// Read from the FIFO
|
||
|
|
while (rx_avail) {
|
||
|
|
|
||
|
|
// Don't read less than 2 bytes if we are using greater than 8 bit characters
|
||
|
|
if (req->bits>8) {
|
||
|
|
((uint16_t*)req->rx_data)[req->rx_num++] = spi->data16;
|
||
|
|
rx_avail -= 1;
|
||
|
|
|
||
|
|
} else {
|
||
|
|
((uint8_t*)req->rx_data)[req->rx_num++] = spi->data8[0];
|
||
|
|
rx_avail -= 1;
|
||
|
|
}
|
||
|
|
rx_avail = ((spi->dma & MXC_F_SPIMSS_DMA_RX_FIFO_CNT) >> MXC_F_SPIMSS_DMA_RX_FIFO_CNT_POS);
|
||
|
|
if ((length - req->rx_num) < rx_avail) {
|
||
|
|
rx_avail = (length - req->rx_num);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
remain = length - req->rx_num;
|
||
|
|
|
||
|
|
if (remain) {
|
||
|
|
if (remain > MXC_SPIMSS_FIFO_DEPTH) {
|
||
|
|
spi->dma = ((spi->dma & ~MXC_F_SPIMSS_DMA_RX_FIFO_CNT) | ((2) << MXC_F_SPIMSS_DMA_RX_FIFO_CNT_POS));
|
||
|
|
} else {
|
||
|
|
spi->dma = ((spi->dma & ~MXC_F_SPIMSS_DMA_RX_FIFO_CNT) | ((remain-1) << MXC_F_SPIMSS_DMA_RX_FIFO_CNT_POS));
|
||
|
|
}
|
||
|
|
|
||
|
|
int_en = 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
// Break out if we've received all the bytes and we're not transmitting
|
||
|
|
if ((req->tx_data == NULL) && (req->rx_num == length)) {
|
||
|
|
spi->ctrl &= ~(MXC_F_SPIMSS_CTRL_IRQE | MXC_F_SPIMSS_CTRL_STR);
|
||
|
|
int_en = 0;
|
||
|
|
mxc_free_lock((uint32_t*)&states[spi_num].req);
|
||
|
|
// Callback if not NULL
|
||
|
|
if (req->callback != NULL) {
|
||
|
|
req->callback(req, E_NO_ERROR);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
// Note:- spi->dma shows the FIFO TX count and FIFO RX count in
|
||
|
|
// Words, while the calculation below is in bytes.
|
||
|
|
if (req->tx_data != NULL) {
|
||
|
|
|
||
|
|
if (req->tx_num < length) {
|
||
|
|
|
||
|
|
// Calculate how many bytes we can write to the FIFO (tx_avail holds that value)
|
||
|
|
tx_avail = MXC_SPIMSS_FIFO_DEPTH - (((spi->dma & MXC_F_SPIMSS_DMA_TX_FIFO_CNT) >> MXC_F_SPIMSS_DMA_TX_FIFO_CNT_POS)); // in bytes
|
||
|
|
|
||
|
|
if ((length - req->tx_num) < tx_avail) {
|
||
|
|
tx_avail = (length - req->tx_num); // This is for the last spin
|
||
|
|
}
|
||
|
|
if (req->bits > 8) {
|
||
|
|
tx_avail &= ~(unsigned)0x1;
|
||
|
|
}
|
||
|
|
// Write the FIFO
|
||
|
|
while (tx_avail) {
|
||
|
|
if (req->bits >8) {
|
||
|
|
spi->data16 = ((uint16_t*)req->tx_data)[req->tx_num++];
|
||
|
|
|
||
|
|
tx_avail -= 1;
|
||
|
|
} else {
|
||
|
|
spi->data8[0] = ((uint8_t*)req->tx_data)[req->tx_num++];
|
||
|
|
tx_avail -=1;
|
||
|
|
}
|
||
|
|
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
remain = length - req->tx_num;
|
||
|
|
|
||
|
|
// If there are values remaining to be transmitted, this portion will get
|
||
|
|
// executed and int_en set, to indicate that this must spin and come back again...
|
||
|
|
if (remain) {
|
||
|
|
if (remain > MXC_SPIMSS_FIFO_DEPTH) { // more tx rounds will happen... Transfer the maximum,
|
||
|
|
spi->dma = ((spi->dma & ~MXC_F_SPIMSS_DMA_TX_FIFO_CNT) | ((MXC_SPIMSS_FIFO_DEPTH) << MXC_F_SPIMSS_DMA_TX_FIFO_CNT_POS));
|
||
|
|
} else { // only one more tx round will be done... Transfer whatever remains,
|
||
|
|
spi->dma = ((spi->dma & ~MXC_F_SPIMSS_DMA_TX_FIFO_CNT) | ((remain) << MXC_F_SPIMSS_DMA_TX_FIFO_CNT_POS));
|
||
|
|
}
|
||
|
|
int_en = 1; // This will act as a trigger for the next round...
|
||
|
|
}
|
||
|
|
|
||
|
|
// Break out if we've transmitted all the bytes and not receiving
|
||
|
|
if ((req->rx_data == NULL) && (req->tx_num == length)) {
|
||
|
|
spi->ctrl &= ~(MXC_F_SPIMSS_CTRL_IRQE | MXC_F_SPIMSS_CTRL_STR);
|
||
|
|
int_en = 0;
|
||
|
|
mxc_free_lock((uint32_t*)&states[spi_num].req);
|
||
|
|
// Callback if not NULL
|
||
|
|
if (req->callback != NULL) {
|
||
|
|
req->callback(req, E_NO_ERROR);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
// Break out once we've transmitted and received all of the data
|
||
|
|
if ((req->rx_num == length) && (req->tx_num == length)) {
|
||
|
|
spi->ctrl &= ~(MXC_F_SPIMSS_CTRL_IRQE | MXC_F_SPIMSS_CTRL_STR);
|
||
|
|
int_en = 0;
|
||
|
|
mxc_free_lock((uint32_t*)&states[spi_num].req);
|
||
|
|
// Callback if not NULL
|
||
|
|
if (req->callback != NULL) {
|
||
|
|
req->callback(req, E_NO_ERROR);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return int_en;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* ************************************************************************* */
|
||
|
|
int SPIMSS_AbortAsync(spimss_req_t *req)
|
||
|
|
{
|
||
|
|
int spi_num;
|
||
|
|
mxc_spimss_regs_t *spi;
|
||
|
|
|
||
|
|
// Check the input parameters
|
||
|
|
if (req == NULL) {
|
||
|
|
return E_BAD_PARAM;
|
||
|
|
}
|
||
|
|
|
||
|
|
// Find the request, set to NULL
|
||
|
|
for (spi_num = 0; spi_num < MXC_SPIMSS_INSTANCES; spi_num++) {
|
||
|
|
if (req == states[spi_num].req) {
|
||
|
|
|
||
|
|
spi = MXC_SPIMSS_GET_SPI(spi_num);
|
||
|
|
|
||
|
|
// Disable interrupts, clear the flags
|
||
|
|
spi->ctrl &= ~(MXC_F_SPIMSS_CTRL_IRQE | MXC_F_SPIMSS_CTRL_STR);
|
||
|
|
|
||
|
|
// Disable and turn off the SPI transaction.
|
||
|
|
spi->ctrl &= ~(MXC_F_SPIMSS_CTRL_SPIEN);
|
||
|
|
|
||
|
|
// Unlock this SPI
|
||
|
|
mxc_free_lock((uint32_t*)&states[spi_num].req);
|
||
|
|
|
||
|
|
// Callback if not NULL
|
||
|
|
if (req->callback != NULL) {
|
||
|
|
req->callback(req, E_ABORT);
|
||
|
|
}
|
||
|
|
return E_NO_ERROR;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return E_BAD_PARAM;
|
||
|
|
}
|
||
|
|
/**@} end of group spimss */
|