642 lines
21 KiB
C
642 lines
21 KiB
C
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/* *****************************************************************************
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* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
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* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Except as contained in this notice, the name of Maxim Integrated
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* Products, Inc. shall not be used except as stated in the Maxim Integrated
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* Products, Inc. Branding Policy.
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*
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* The mere transfer of this software does not imply any licenses
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* of trade secrets, proprietary technology, copyrights, patents,
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* trademarks, maskwork rights, or any other form of intellectual
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* property whatsoever. Maxim Integrated Products, Inc. retains all
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* ownership rights.
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*
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* $Date: 2019-06-25 10:15:10 -0500 (Tue, 25 Jun 2019) $
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* $Revision: 44277 $
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*
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**************************************************************************** */
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/* **** Includes **** */
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#include <string.h>
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#include "mxc_config.h"
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#include "mxc_assert.h"
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#include "mxc_sys.h"
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#include "tmr_utils.h"
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#include "mxc_lock.h"
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#include "spi17y.h"
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/* **** Definitions **** */
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/* **** Globals **** */
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typedef struct {
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spi17y_req_t *req;
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int started;
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unsigned last_size;
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unsigned deass;
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} spi17y_req_state_t;
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static spi17y_req_state_t states[MXC_SPI17Y_INSTANCES];
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/* **** Functions **** */
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static int SPI17Y_TransSetup(mxc_spi17y_regs_t *spi, spi17y_req_t *req, int master);
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static int SPI17Y_MasterTransHandler(mxc_spi17y_regs_t *spi, spi17y_req_t *req, uint8_t async);
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static int SPI17Y_TransHandler(mxc_spi17y_regs_t *spi, spi17y_req_t *req, uint8_t async);
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static int SPI17Y_SlaveTransHandler(mxc_spi17y_regs_t *spi, spi17y_req_t *req, uint8_t async);
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/* ************************************************************************** */
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int SPI17Y_Init(mxc_spi17y_regs_t *spi, unsigned int mode, unsigned int freq,
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const sys_cfg_spi17y_t* sys_cfg)
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{
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uint32_t freq_div;
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int spi_num, error, hi_clk, lo_clk, scale;
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spi_num = MXC_SPI17Y_GET_IDX(spi);
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MXC_ASSERT(spi_num >= 0);
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if (mode > 3) {
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return E_BAD_PARAM;
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}
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if ((error = SYS_SPI17Y_Init(spi, sys_cfg)) != E_NO_ERROR) {
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return error;
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}
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states[spi_num].req = NULL;
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states[spi_num].last_size = 0;
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states[spi_num].deass = 1;
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// Enable SPI17Y
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spi->ctrl0 = (MXC_F_SPI17Y_CTRL0_EN);
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spi->ss_time = ((0x1 << MXC_F_SPI17Y_SS_TIME_PRE_POS) |
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(0x1 << MXC_F_SPI17Y_SS_TIME_POST_POS) |
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(0x1 << MXC_F_SPI17Y_SS_TIME_INACT_POS));
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// Check if frequency is too high
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if (freq > PeripheralClock) {
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return E_BAD_PARAM;
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}
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// Set the clock high and low
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freq_div = PeripheralClock/ (freq);
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hi_clk = freq_div/2;
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lo_clk = freq_div/2;
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scale = 0;
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if (freq_div %2) {
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hi_clk +=1;
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}
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while (hi_clk > 16 && scale < 9) {
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hi_clk /= 2;
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lo_clk /=2;
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scale ++;
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}
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spi->clk_cfg = ((lo_clk << MXC_F_SPI17Y_CLK_CFG_LO_POS) |
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(hi_clk << MXC_F_SPI17Y_CLK_CFG_HI_POS));
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MXC_SETFIELD(spi->clk_cfg, MXC_F_SPI17Y_CLK_CFG_SCALE, (scale << MXC_F_SPI17Y_CLK_CFG_SCALE_POS));
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// Set the mode
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spi->ctrl2 = (mode << MXC_F_SPI17Y_CTRL2_CPHA_POS);
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// Clear the interrupts
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spi->int_fl = spi->int_fl;
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return E_NO_ERROR;
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}
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/* ************************************************************************* */
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int SPI17Y_Shutdown(mxc_spi17y_regs_t *spi)
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{
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int spi_num, err;
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spi17y_req_t *temp_req;
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// Disable and clear interrupts
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spi->int_en = 0;
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spi->int_fl = spi->int_fl;
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// Disable SPI17Y and FIFOS
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spi->ctrl0 &= ~(MXC_F_SPI17Y_CTRL0_EN);
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spi->dma &= ~(MXC_F_SPI17Y_DMA_TX_FIFO_EN | MXC_F_SPI17Y_DMA_RX_FIFO_EN);
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// Call all of the pending callbacks for this SPI17Y
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spi_num = MXC_SPI17Y_GET_IDX(spi);
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if (states[spi_num].req != NULL) {
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// Save the request
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temp_req = states[spi_num].req;
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// Unlock this SPI17Y
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mxc_free_lock((uint32_t*)&states[spi_num].req);
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// Callback if not NULL
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if (temp_req->callback != NULL) {
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temp_req->callback(temp_req, E_SHUTDOWN);
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}
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}
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// Clear registers
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spi->ctrl0 = 0;
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spi->ctrl1 = 0;
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spi->ctrl2 = 0;
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spi->ss_time = 0;
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// Clear system level configurations
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if ((err = SYS_SPI17Y_Shutdown(spi)) != E_NO_ERROR) {
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return err;
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}
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return E_NO_ERROR;
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}
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/* ************************************************************************** */
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int SPI17Y_TransSetup(mxc_spi17y_regs_t *spi, spi17y_req_t *req, int master)
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{
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int spi_num;
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if ((req->tx_data == NULL) && (req->rx_data == NULL)) {
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return E_BAD_PARAM;
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}
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if ((req->width > SPI17Y_WIDTH_1) && (req->tx_data != NULL) && (req->rx_data != NULL)) {
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return E_BAD_PARAM;
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}
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// HW has problem with these two character sizes
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if (req->bits == 1 || req->bits == 9) {
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return E_BAD_PARAM;
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}
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spi_num = MXC_SPI17Y_GET_IDX(spi);
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MXC_ASSERT(spi_num >= 0);
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MXC_ASSERT(req->ssel < MXC_SPI17Y_SS_INSTANCES);
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req->tx_num = 0;
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req->rx_num = 0;
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if (req->len == 0) {
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return E_NO_ERROR;
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}
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states[spi_num].req = req;
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states[spi_num].started = 0;
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// HW requires disabling/renabling SPI block at end of each transaction (when SS is inactive).
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if (states[spi_num].deass == 1) {
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spi->ctrl0 &= ~(MXC_F_SPI17Y_CTRL0_EN);
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}
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if (master) {
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// Enable master mode
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spi->ctrl0 |= MXC_F_SPI17Y_CTRL0_MASTER;
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// Setup the slave select
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MXC_SETFIELD(spi->ctrl0, MXC_F_SPI17Y_CTRL0_SS, ((0x1 << req->ssel) << MXC_F_SPI17Y_CTRL0_SS_POS));
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spi->ctrl2 |= ((req->ssel_pol << req->ssel)<<MXC_F_SPI17Y_CTRL2_SS_POL_POS);
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} else {
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// Enable slave mode
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spi->ctrl0 &= ~MXC_F_SPI17Y_CTRL0_MASTER;
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// Setup the slave select
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spi->ctrl2 |= ((req->ssel_pol << 0)<<MXC_F_SPI17Y_CTRL2_SS_POL_POS);
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}
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if ((req->bits != states[spi_num].last_size)) {
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// Setup the character size
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// Master should only change character size at the end of a transaction. No restrictions on when slave can change.
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if (!master || (!(spi->stat & MXC_F_SPI17Y_STAT_BUSY) && (states[spi_num].deass == 1)) || !(spi->ctrl0 & MXC_F_SPI17Y_CTRL0_EN)) {
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//disable spi to change transfer size
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spi->ctrl0 &= ~(MXC_F_SPI17Y_CTRL0_EN);
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// set bit size
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states[spi_num].last_size = req->bits;
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if (req->bits <16) {
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MXC_SETFIELD(spi->ctrl2, MXC_F_SPI17Y_CTRL2_NUMBITS, req->bits << MXC_F_SPI17Y_CTRL2_NUMBITS_POS);
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} else {
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MXC_SETFIELD(spi->ctrl2, MXC_F_SPI17Y_CTRL2_NUMBITS, 0 << MXC_F_SPI17Y_CTRL2_NUMBITS_POS);
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}
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} else {
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// cant change transfer size while spi is busy
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return E_BAD_STATE;
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}
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}
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// Setup the data width
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if (req->width == SPI17Y_WIDTH_4) {
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MXC_SETFIELD(spi->ctrl2, MXC_F_SPI17Y_CTRL2_DATA_WIDTH, MXC_S_SPI17Y_CTRL2_DATA_WIDTH_QUAD);
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} else if (req->width == SPI17Y_WIDTH_2) {
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MXC_SETFIELD(spi->ctrl2, MXC_F_SPI17Y_CTRL2_DATA_WIDTH, MXC_S_SPI17Y_CTRL2_DATA_WIDTH_DUAL);
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} else {
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MXC_SETFIELD(spi->ctrl2, MXC_F_SPI17Y_CTRL2_DATA_WIDTH, MXC_S_SPI17Y_CTRL2_DATA_WIDTH_MONO);
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}
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// Setup the number of characters to transact
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if (req->len > (MXC_F_SPI17Y_CTRL1_TX_NUM_CHAR >> MXC_F_SPI17Y_CTRL1_TX_NUM_CHAR_POS)) {
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return E_BAD_PARAM;
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}
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if (req->rx_data != NULL) {
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// The TX_NUM field is used for both RX and TX length when in 4-wire mode.
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if(req->width == SPI17Y_WIDTH_1) {
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MXC_SETFIELD(spi->ctrl1, MXC_F_SPI17Y_CTRL1_TX_NUM_CHAR,
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req->len << MXC_F_SPI17Y_CTRL1_TX_NUM_CHAR_POS);
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} else {
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MXC_SETFIELD(spi->ctrl1, MXC_F_SPI17Y_CTRL1_RX_NUM_CHAR,
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req->len << MXC_F_SPI17Y_CTRL1_RX_NUM_CHAR_POS);
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}
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spi->dma |= MXC_F_SPI17Y_DMA_RX_FIFO_EN;
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} else {
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spi->ctrl1 &= ~(MXC_F_SPI17Y_CTRL1_RX_NUM_CHAR);
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spi->dma &= ~(MXC_F_SPI17Y_DMA_RX_FIFO_EN);
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}
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// Must use TXFIFO and NUM in full duplex
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if (req->width == SPI17Y_WIDTH_1
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&& !((spi->ctrl2 & MXC_F_SPI17Y_CTRL2_THREE_WIRE)>> MXC_F_SPI17Y_CTRL2_THREE_WIRE_POS)) {
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if (req->tx_data == NULL) {
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// Must have something to send, so we'll use the rx_data buffer initialized to 0.
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memset(req->rx_data, 0, (req->bits > 8 ? req->len << 1 : req->len));
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req->tx_data = req->rx_data;
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req->tx_num = 0;
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}
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}
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if(req->tx_data != NULL) {
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MXC_SETFIELD(spi->ctrl1, MXC_F_SPI17Y_CTRL1_TX_NUM_CHAR,
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req->len << MXC_F_SPI17Y_CTRL1_TX_NUM_CHAR_POS);
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spi->dma |= MXC_F_SPI17Y_DMA_TX_FIFO_EN;
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} else {
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spi->dma &= ~(MXC_F_SPI17Y_DMA_TX_FIFO_EN);
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}
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spi->dma |= MXC_F_SPI17Y_DMA_TX_FIFO_CLEAR | MXC_F_SPI17Y_DMA_RX_FIFO_CLEAR;
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spi->ctrl0 |= (MXC_F_SPI17Y_CTRL0_EN);
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states[spi_num].deass = req->deass;
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// Clear master done flag
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spi->int_fl = MXC_F_SPI17Y_INT_FL_M_DONE;
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return E_NO_ERROR;
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}
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/* ************************************************************************** */
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void SPI17Y_Handler(mxc_spi17y_regs_t *spi)
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{
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int spi_num, rx_avail;
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uint32_t flags;
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// Clear the interrupt flags
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spi->int_en = 0;
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flags = spi->int_fl;
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spi->int_fl = flags;
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spi_num = MXC_SPI17Y_GET_IDX(spi);
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// Figure out if this SPI17Y has an active request
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if ((states[spi_num].req != NULL) && (flags)) {
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if ((spi->ctrl0 & MXC_F_SPI17Y_CTRL0_MASTER)>> MXC_F_SPI17Y_CTRL0_MASTER_POS) {
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do {
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SPI17Y_MasterTransHandler(spi, states[spi_num].req, 1);
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rx_avail = (spi->dma & MXC_F_SPI17Y_DMA_RX_FIFO_CNT) >> MXC_F_SPI17Y_DMA_RX_FIFO_CNT_POS;
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} while ((states[spi_num].req->rx_data != NULL) && (rx_avail > (spi->dma & MXC_F_SPI17Y_DMA_RX_FIFO_LEVEL)
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>>MXC_F_SPI17Y_DMA_RX_FIFO_LEVEL_POS));
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} else {
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do {
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SPI17Y_SlaveTransHandler(spi, states[spi_num].req, 1);
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rx_avail = (spi->dma & MXC_F_SPI17Y_DMA_RX_FIFO_CNT) >> MXC_F_SPI17Y_DMA_RX_FIFO_CNT_POS;
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} while ((states[spi_num].req->rx_data != NULL) && (rx_avail > (spi->dma & MXC_F_SPI17Y_DMA_RX_FIFO_LEVEL)
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>>MXC_F_SPI17Y_DMA_RX_FIFO_LEVEL_POS));
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}
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}
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}
|
||
|
|
|
||
|
|
/* ************************************************************************** */
|
||
|
|
int SPI17Y_MasterTrans(mxc_spi17y_regs_t *spi,spi17y_req_t *req)
|
||
|
|
{
|
||
|
|
int error;
|
||
|
|
if ((error =SPI17Y_TransSetup(spi, req, 1)) != E_NO_ERROR) {
|
||
|
|
return error;
|
||
|
|
}
|
||
|
|
req->callback = NULL;
|
||
|
|
|
||
|
|
while (SPI17Y_MasterTransHandler(spi,req,0)==0) {
|
||
|
|
}
|
||
|
|
|
||
|
|
while (!(spi->int_fl & MXC_F_SPI17Y_INT_FL_M_DONE)) {
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
return E_NO_ERROR;
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
/* ************************************************************************** */
|
||
|
|
int SPI17Y_SlaveTrans(mxc_spi17y_regs_t *spi, spi17y_req_t *req)
|
||
|
|
{
|
||
|
|
int error;
|
||
|
|
if ((error =SPI17Y_TransSetup(spi, req,0)) != E_NO_ERROR) {
|
||
|
|
return error;
|
||
|
|
}
|
||
|
|
req->callback = NULL;
|
||
|
|
|
||
|
|
while (SPI17Y_SlaveTransHandler(spi,req,0)==0) {
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
return E_NO_ERROR;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* ************************************************************************** */
|
||
|
|
int SPI17Y_MasterTransAsync(mxc_spi17y_regs_t *spi, spi17y_req_t *req)
|
||
|
|
{
|
||
|
|
int error;
|
||
|
|
if ((error =SPI17Y_TransSetup(spi, req, 1))!= E_NO_ERROR) {
|
||
|
|
return error;
|
||
|
|
}
|
||
|
|
|
||
|
|
SPI17Y_MasterTransHandler(spi,req, 1);
|
||
|
|
|
||
|
|
return E_NO_ERROR;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* ************************************************************************** */
|
||
|
|
int SPI17Y_SlaveTransAsync(mxc_spi17y_regs_t *spi, spi17y_req_t *req)
|
||
|
|
{
|
||
|
|
int error;
|
||
|
|
if ((error =SPI17Y_TransSetup(spi, req, 0)) != E_NO_ERROR) {
|
||
|
|
return error;
|
||
|
|
}
|
||
|
|
|
||
|
|
SPI17Y_SlaveTransHandler(spi,req, 1);
|
||
|
|
|
||
|
|
|
||
|
|
return E_NO_ERROR;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* ************************************************************************** */
|
||
|
|
int SPI17Y_MasterTransHandler(mxc_spi17y_regs_t *spi, spi17y_req_t *req,uint8_t async)
|
||
|
|
{
|
||
|
|
int retval;
|
||
|
|
int spi_num;
|
||
|
|
|
||
|
|
spi_num = MXC_SPI17Y_GET_IDX(spi);
|
||
|
|
|
||
|
|
// Leave slave select asserted at the end of the transaction
|
||
|
|
if (!req->deass) {
|
||
|
|
spi->ctrl0 |= MXC_F_SPI17Y_CTRL0_SS_CTRL;
|
||
|
|
}
|
||
|
|
|
||
|
|
retval = SPI17Y_TransHandler(spi,req, async);
|
||
|
|
|
||
|
|
if (!states[spi_num].started) {
|
||
|
|
spi->ctrl0 |= MXC_F_SPI17Y_CTRL0_START;
|
||
|
|
states[spi_num].started = 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
// Deassert slave select at the end of the transaction
|
||
|
|
if (req->deass) {
|
||
|
|
spi->ctrl0 &= ~MXC_F_SPI17Y_CTRL0_SS_CTRL;
|
||
|
|
}
|
||
|
|
|
||
|
|
return retval;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* ************************************************************************** */
|
||
|
|
int SPI17Y_SlaveTransHandler(mxc_spi17y_regs_t *spi, spi17y_req_t *req, uint8_t async)
|
||
|
|
{
|
||
|
|
return SPI17Y_TransHandler(spi,req, async);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* ************************************************************************** */
|
||
|
|
// Returns non-zero if transactions is complete, or 0 if not.
|
||
|
|
int SPI17Y_TransHandler(mxc_spi17y_regs_t *spi, spi17y_req_t *req, uint8_t async)
|
||
|
|
{
|
||
|
|
|
||
|
|
unsigned tx_avail, rx_avail;
|
||
|
|
int remain, spi_num;
|
||
|
|
uint32_t int_en =0;
|
||
|
|
uint32_t length =0;
|
||
|
|
spi_num = MXC_SPI17Y_GET_IDX(spi);
|
||
|
|
|
||
|
|
// Read/write 2x number of bytes if larger character size
|
||
|
|
if (req->bits > 8) {
|
||
|
|
length = req->len*2;
|
||
|
|
} else {
|
||
|
|
length = req->len;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (req->tx_data != NULL) {
|
||
|
|
// Need to know when all bytes are transmitted, so the callback can be triggered.
|
||
|
|
int_en |= MXC_F_SPI17Y_INT_EN_TX_EMPTY;
|
||
|
|
|
||
|
|
// Calculate how many bytes we can write to the FIFO
|
||
|
|
tx_avail = MXC_SPI17Y_FIFO_DEPTH - ((spi->dma & MXC_F_SPI17Y_DMA_TX_FIFO_CNT) >>
|
||
|
|
MXC_F_SPI17Y_DMA_TX_FIFO_CNT_POS);
|
||
|
|
if ((length - req->tx_num) < tx_avail) {
|
||
|
|
tx_avail = (length - req->tx_num);
|
||
|
|
}
|
||
|
|
if (req->bits > 8) {
|
||
|
|
tx_avail &= ~(unsigned)0x1;
|
||
|
|
}
|
||
|
|
// Write the FIFO
|
||
|
|
while (tx_avail) {
|
||
|
|
if (tx_avail > 3) {
|
||
|
|
memcpy((void*)&spi->data32,&((uint8_t*)req->tx_data)[req->tx_num], 4);
|
||
|
|
|
||
|
|
tx_avail -= 4;
|
||
|
|
req->tx_num += 4;
|
||
|
|
|
||
|
|
} else if (tx_avail > 1) {
|
||
|
|
memcpy((void*)&spi->data16[0],&((uint8_t*)req->tx_data)[req->tx_num], 2);
|
||
|
|
|
||
|
|
tx_avail -= 2;
|
||
|
|
req->tx_num += 2;
|
||
|
|
|
||
|
|
} else if (req->bits<=8) {
|
||
|
|
spi->data8[0] = ((uint8_t*)req->tx_data)[req->tx_num++];
|
||
|
|
|
||
|
|
tx_avail -= 1;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
remain = length - req->tx_num;
|
||
|
|
|
||
|
|
// Set the TX interrupts
|
||
|
|
if (remain) {
|
||
|
|
if (remain > MXC_SPI17Y_FIFO_DEPTH) {
|
||
|
|
// Set the TX FIFO almost empty interrupt if we have to refill
|
||
|
|
spi->dma = ((spi->dma & ~MXC_F_SPI17Y_DMA_TX_FIFO_LEVEL) |
|
||
|
|
((MXC_SPI17Y_FIFO_DEPTH) << MXC_F_SPI17Y_DMA_TX_FIFO_LEVEL_POS));
|
||
|
|
} else {
|
||
|
|
|
||
|
|
spi->dma = ((spi->dma & ~MXC_F_SPI17Y_DMA_TX_FIFO_LEVEL) |
|
||
|
|
((remain) << MXC_F_SPI17Y_DMA_TX_FIFO_LEVEL_POS));
|
||
|
|
}
|
||
|
|
int_en |= MXC_F_SPI17Y_INT_EN_TX_THRESH;
|
||
|
|
|
||
|
|
}
|
||
|
|
// Break out if we've transmitted all the bytes and not receiving
|
||
|
|
if ((req->rx_data == NULL) && (req->tx_num == length) && ((spi->dma & MXC_F_SPI17Y_DMA_TX_FIFO_CNT) == 0)) {
|
||
|
|
spi->int_en = 0;
|
||
|
|
int_en = 0;
|
||
|
|
mxc_free_lock((uint32_t*)&states[spi_num].req);
|
||
|
|
// Callback if not NULL
|
||
|
|
if (req->callback != NULL) {
|
||
|
|
req->callback(req, E_NO_ERROR);
|
||
|
|
}
|
||
|
|
return 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
// Read the RX FIFO
|
||
|
|
if (req->rx_data != NULL) {
|
||
|
|
|
||
|
|
// Wait for there to be data in the RX FIFO
|
||
|
|
rx_avail = (spi->dma & MXC_F_SPI17Y_DMA_RX_FIFO_CNT) >> MXC_F_SPI17Y_DMA_RX_FIFO_CNT_POS;
|
||
|
|
if ((length - req->rx_num) < rx_avail) {
|
||
|
|
rx_avail = (length - req->rx_num);
|
||
|
|
}
|
||
|
|
if (req->bits <= 8 || rx_avail >= 2) {
|
||
|
|
// Read from the FIFO
|
||
|
|
while (rx_avail) {
|
||
|
|
if (rx_avail > 3) {
|
||
|
|
memcpy(&((uint8_t*)req->rx_data)[req->rx_num], (void*)&spi->data32, 4);
|
||
|
|
rx_avail -= 4;
|
||
|
|
req->rx_num += 4;
|
||
|
|
|
||
|
|
} else if (rx_avail > 1) {
|
||
|
|
memcpy(&((uint8_t*)req->rx_data)[req->rx_num], (void*)&spi->data16[0], 2);
|
||
|
|
rx_avail -= 2;
|
||
|
|
req->rx_num += 2;
|
||
|
|
|
||
|
|
} else {
|
||
|
|
((uint8_t*)req->rx_data)[req->rx_num++] = spi->data8[0];
|
||
|
|
rx_avail -= 1;
|
||
|
|
}
|
||
|
|
// Don't read less than 2 bytes if we are using greater than 8 bit characters
|
||
|
|
if (rx_avail == 1 && req->bits > 8) {
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
remain = length - req->rx_num;
|
||
|
|
if (remain) {
|
||
|
|
if (remain > MXC_SPI17Y_FIFO_DEPTH) {
|
||
|
|
spi->dma = ((spi->dma & ~MXC_F_SPI17Y_DMA_RX_FIFO_LEVEL) |
|
||
|
|
((2) << MXC_F_SPI17Y_DMA_RX_FIFO_LEVEL_POS));
|
||
|
|
} else {
|
||
|
|
spi->dma = ((spi->dma & ~MXC_F_SPI17Y_DMA_RX_FIFO_LEVEL) |
|
||
|
|
((remain-1) << MXC_F_SPI17Y_DMA_RX_FIFO_LEVEL_POS));
|
||
|
|
}
|
||
|
|
int_en |= MXC_F_SPI17Y_INT_EN_RX_THRESH;
|
||
|
|
}
|
||
|
|
|
||
|
|
// Break out if we've received all the bytes and we're not transmitting
|
||
|
|
if ((req->tx_data == NULL) && (req->rx_num == length)) {
|
||
|
|
spi->int_en = 0;
|
||
|
|
int_en = 0;
|
||
|
|
mxc_free_lock((uint32_t*)&states[spi_num].req);
|
||
|
|
// Callback if not NULL
|
||
|
|
if (req->callback != NULL) {
|
||
|
|
req->callback(req, E_NO_ERROR);
|
||
|
|
}
|
||
|
|
return 1;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
// Break out once we've transmitted and received all of the data
|
||
|
|
if ((req->rx_num == length) && (req->tx_num == length) && ((spi->dma & MXC_F_SPI17Y_DMA_TX_FIFO_CNT) == 0)) {
|
||
|
|
spi->int_en = 0;
|
||
|
|
int_en = 0;
|
||
|
|
mxc_free_lock((uint32_t*)&states[spi_num].req);
|
||
|
|
// Callback if not NULL
|
||
|
|
if (req->callback != NULL) {
|
||
|
|
req->callback(req, E_NO_ERROR);
|
||
|
|
}
|
||
|
|
return 1;
|
||
|
|
}
|
||
|
|
if(async){
|
||
|
|
spi->int_en = int_en;
|
||
|
|
}
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* ************************************************************************* */
|
||
|
|
int SPI17Y_AbortAsync(spi17y_req_t *req)
|
||
|
|
{
|
||
|
|
int spi_num;
|
||
|
|
mxc_spi17y_regs_t *spi;
|
||
|
|
|
||
|
|
// Check the input parameters
|
||
|
|
if (req == NULL) {
|
||
|
|
return E_BAD_PARAM;
|
||
|
|
}
|
||
|
|
|
||
|
|
// Find the request, set to NULL
|
||
|
|
for (spi_num = 0; spi_num < MXC_SPI17Y_INSTANCES; spi_num++) {
|
||
|
|
if (req == states[spi_num].req) {
|
||
|
|
|
||
|
|
spi = MXC_SPI17Y_GET_SPI17Y(spi_num);
|
||
|
|
|
||
|
|
// Disable interrupts, clear the flags
|
||
|
|
spi->int_en = 0;
|
||
|
|
spi->int_fl = spi->int_fl;
|
||
|
|
|
||
|
|
// Reset the SPI17Y to cancel the on ongoing transaction
|
||
|
|
spi->ctrl0 &= ~(MXC_F_SPI17Y_CTRL0_EN);
|
||
|
|
spi->ctrl0 |= (MXC_F_SPI17Y_CTRL0_EN);
|
||
|
|
|
||
|
|
// Unlock this SPI17Y
|
||
|
|
mxc_free_lock((uint32_t*)&states[spi_num].req);
|
||
|
|
|
||
|
|
// Callback if not NULL
|
||
|
|
if (req->callback != NULL) {
|
||
|
|
req->callback(req, E_ABORT);
|
||
|
|
}
|
||
|
|
|
||
|
|
return E_NO_ERROR;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return E_BAD_PARAM;
|
||
|
|
}
|
||
|
|
|
||
|
|
// *****************************************************************************
|
||
|
|
void SPI17Y_Enable(mxc_spi17y_regs_t* spi)
|
||
|
|
{
|
||
|
|
spi->ctrl0 |= (MXC_F_SPI17Y_CTRL0_EN);
|
||
|
|
}
|
||
|
|
|
||
|
|
// *****************************************************************************
|
||
|
|
void SPI17Y_Disable(mxc_spi17y_regs_t* spi)
|
||
|
|
{
|
||
|
|
spi->ctrl0 &= ~(MXC_F_SPI17Y_CTRL0_EN);
|
||
|
|
}
|
||
|
|
|
||
|
|
// *****************************************************************************
|
||
|
|
void SPI17Y_Clear_fifo(mxc_spi17y_regs_t* spi)
|
||
|
|
{
|
||
|
|
spi->dma |= MXC_F_SPI17Y_DMA_TX_FIFO_CLEAR | MXC_F_SPI17Y_DMA_RX_FIFO_CLEAR;
|
||
|
|
}
|