96 lines
3.8 KiB
Plaintext
96 lines
3.8 KiB
Plaintext
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/*
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** ###################################################################
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** Processors: MIMXRT1052CVJ5B
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** MIMXRT1052CVL5B
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** MIMXRT1052DVJ6B
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** MIMXRT1052DVL6B
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**
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** Compiler: IAR ANSI C/C++ Compiler for ARM
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** Reference manual: IMXRT1050RM Rev.1, 03/2018
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** Version: rev. 1.0, 2018-09-21
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** Build: b180921
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**
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** Abstract:
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** Linker file for the IAR ANSI C/C++ Compiler for ARM
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**
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** Copyright 2016 Freescale Semiconductor, Inc.
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** Copyright 2016-2018 NXP
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** All rights reserved.
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**
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** SPDX-License-Identifier: BSD-3-Clause
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**
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** http: www.nxp.com
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** mail: support@nxp.com
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**
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** ###################################################################
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*/
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define symbol m_interrupts_start = 0x70002000;
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define symbol m_interrupts_end = 0x700023FF;
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define symbol m_text_start = 0x70002400;
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define symbol m_text_end = 0x73FFFFFF;
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define symbol m_data_start = 0x20000000;
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define symbol m_data_end = 0x2001FFFF;
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define symbol m_data2_start = 0x20200000;
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define symbol m_data2_end = 0x2023FFFF;
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define exported symbol m_boot_hdr_conf_start = 0x70000000;
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define symbol m_boot_hdr_ivt_start = 0x70001000;
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define symbol m_boot_hdr_boot_data_start = 0x70001020;
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define symbol m_boot_hdr_dcd_data_start = 0x70001030;
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/* Sizes */
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if (isdefinedsymbol(__stack_size__)) {
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define symbol __size_cstack__ = __stack_size__;
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} else {
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define symbol __size_cstack__ = 0x0400;
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}
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if (isdefinedsymbol(__heap_size__)) {
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define symbol __size_heap__ = __heap_size__;
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} else {
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define symbol __size_heap__ = 0x0400;
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}
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define exported symbol __VECTOR_TABLE = m_interrupts_start;
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define exported symbol __VECTOR_RAM = m_interrupts_start;
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define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0;
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define exported symbol __RTT_HEAP_END = m_data2_end;
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define memory mem with size = 4G;
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define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
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| mem:[from m_text_start to m_text_end];
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define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__];
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define region DATA2_region = mem:[from m_data2_start to m_data2_end];
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define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];
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define block CSTACK with alignment = 8, size = __size_cstack__ { };
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define block HEAP with alignment = 8, size = __size_heap__ { };
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define block RW { readwrite };
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define block ZI { zi };
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define block NCACHE_VAR { section NonCacheable , section NonCacheable.init };
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initialize by copy { readwrite, section .textrw };
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do not initialize { section .noinit };
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place at address mem: m_interrupts_start { readonly section .intvec };
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place at address mem:m_boot_hdr_conf_start { section .boot_hdr.conf };
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place at address mem:m_boot_hdr_ivt_start { section .boot_hdr.ivt };
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place at address mem:m_boot_hdr_boot_data_start { readonly section .boot_hdr.boot_data };
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place at address mem:m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_data };
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keep{ section .boot_hdr.conf, section .boot_hdr.ivt, section .boot_hdr.boot_data, section .boot_hdr.dcd_data };
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place in TEXT_region { readonly };
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place in DATA_region { block RW };
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place in DATA_region { block ZI };
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place in DATA_region { last block HEAP };
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place in DATA_region { block NCACHE_VAR };
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place in CSTACK_region { block CSTACK };
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