90 lines
4.0 KiB
C
90 lines
4.0 KiB
C
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-03-18 shelton first version
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*/
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#ifndef __DRV_ETH_H__
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#define __DRV_ETH_H__
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#include <rtthread.h>
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#include <rthw.h>
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#include <rtdevice.h>
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#include <board.h>
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#define CRYSTAL_ON_PHY 0 /* phy does not with crystal */
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/* the phy basic control register */
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#define PHY_BASIC_CONTROL_REG 0x00U
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#define PHY_RESET_MASK (1<<15)
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#define PHY_AUTO_NEGOTIATION_MASK (1<<12)
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/* the phy basic status register */
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#define PHY_BASIC_STATUS_REG 0x01U
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#define PHY_LINKED_STATUS_MASK (1<<2)
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#define PHY_AUTONEGO_COMPLETE_MASK (1<<5)
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/* the phy id one register */
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#define PHY_ID1_REG 0x02U
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/* the phy id two register */
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#define PHY_ID2_REG 0x03U
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/* the phy auto-negotiate advertise register */
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#define PHY_AUTONEG_ADVERTISE_REG 0x04U
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#if defined (PHY_USING_DM9162)
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#define PHY_CONTROL_REG (0x00) /*!< basic mode control register */
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#define PHY_STATUS_REG (0x01) /*!< basic mode status register */
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#define PHY_SPECIFIED_CS_REG (0x11) /*!< specified configuration and status register */
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/* phy control register */
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#define PHY_AUTO_NEGOTIATION_BIT (0x1000) /*!< enable auto negotiation */
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#define PHY_LOOPBACK_BIT (0x4000) /*!< enable loopback */
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#define PHY_RESET_BIT (0x8000) /*!< reset phy */
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/* phy status register */
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#define PHY_LINKED_STATUS_BIT (0x0004) /*!< link status */
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#define PHY_NEGO_COMPLETE_BIT (0x0020) /*!< auto negotiation complete */
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/* phy specified control/status register */
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#define PHY_FULL_DUPLEX_100MBPS_BIT (0x8000) /*!< full duplex 100 mbps */
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#define PHY_HALF_DUPLEX_100MBPS_BIT (0x4000) /*!< half duplex 100 mbps */
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#define PHY_FULL_DUPLEX_10MBPS_BIT (0x2000) /*!< full duplex 10 mbps */
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#define PHY_HALF_DUPLEX_10MBPS_BIT (0x1000) /*!< half duplex 10 mbps */
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#define PHY_DUPLEX_MODE (PHY_FULL_DUPLEX_100MBPS_BIT | PHY_FULL_DUPLEX_10MBPS_BIT) /*!< full duplex mode */
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#define PHY_SPEED_MODE (PHY_FULL_DUPLEX_10MBPS_BIT | PHY_HALF_DUPLEX_10MBPS_BIT) /*!< 10 mbps */
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/* the phy interrupt source flag register. */
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#define PHY_INTERRUPT_FLAG_REG 0x15U
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/* the phy interrupt mask register. */
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#define PHY_INTERRUPT_MASK_REG 0x15U
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#define PHY_LINK_CHANGE_FLAG (1<<2)
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#define PHY_LINK_CHANGE_MASK (1<<9)
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#define PHY_INT_MASK 0
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#elif defined (PHY_USING_DP83848)
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#define PHY_CONTROL_REG (0x00) /*!< basic mode control register */
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#define PHY_STATUS_REG (0x01) /*!< basic mode status register */
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#define PHY_SPECIFIED_CS_REG (0x10) /*!< phy status register */
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/* phy control register */
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#define PHY_AUTO_NEGOTIATION_BIT (0x1000) /*!< enable auto negotiation */
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#define PHY_LOOPBACK_BIT (0x4000) /*!< enable loopback */
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#define PHY_RESET_BIT (0x8000) /*!< reset phy */
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/* phy status register */
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#define PHY_LINKED_STATUS_BIT (0x0004) /*!< link status */
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#define PHY_NEGO_COMPLETE_BIT (0x0020) /*!< auto negotiation complete */
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#define PHY_DUPLEX_MODE (0x0004) /*!< full duplex mode */
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#define PHY_SPEED_MODE (0x0002) /*!< 10 mbps */
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/* the phy interrupt source flag register. */
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#define PHY_INTERRUPT_FLAG_REG 0x12U
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#define PHY_LINK_CHANGE_FLAG (1<<13)
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/* the phy interrupt control register. */
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#define PHY_INTERRUPT_CTRL_REG 0x11U
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#define PHY_INTERRUPT_EN ((1<<0)|(1<<1))
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/* the phy interrupt mask register. */
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#define PHY_INTERRUPT_MASK_REG 0x12U
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#define PHY_INT_MASK (1<<5)
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#endif
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#endif /* __DRV_ETH_H__ */
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