637 lines
21 KiB
C
637 lines
21 KiB
C
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/**
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******************************************************************************
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* @brief SDIO functions of the firmware library.
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******************************************************************************
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*/
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#ifdef GD32F10X_HD
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/* Includes ------------------------------------------------------------------*/
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#include "gd32f10x_sdio.h"
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#include "gd32f10x_rcc.h"
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/** @addtogroup GD32F10x_Firmware
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* @{
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*/
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/** @defgroup SDIO
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* @brief SDIO driver modules
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* @{
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*/
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/** @defgroup SDIO_Private_Defines
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* @{
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*/
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/* SDIO registers bit mask */
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/* CLKCTLR register mask */
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#define CLKCTLR_CLEAR_MASK ((uint32_t)0xFFFF8100)
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/* POWER_PWRSTATE mask */
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#define POWER_PWRSTATE_MASK ((uint32_t)0xFFFFFFFC)
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/* DTCTLR register mask */
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#define DTCTLR_CLEAR_MASK ((uint32_t)0xFFFFFF08)
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/* CMD register mask */
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#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800)
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/* SDIO RESP Registers Address */
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#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))
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/**
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* @}
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*/
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/** @defgroup SDIO_Private_Functions
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* @{
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*/
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/**
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* @brief Deinitialize the SDIO .
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* @param None
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* @retval None
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*/
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void SDIO_DeInit(void)
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{
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SDIO->POWER = 0x00000000;
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SDIO->CLKCTLR = 0x00000000;
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SDIO->PARA = 0x00000000;
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SDIO->CMD = 0x00000000;
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SDIO->DTTR = 0x00000000;
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SDIO->DTLEN = 0x00000000;
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SDIO->DTCTLR = 0x00000000;
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SDIO->ICR = 0x00C007FF;
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SDIO->IER = 0x00000000;
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}
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/**
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* @brief Initialize the SDIO .
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* @param SDIO_InitParaStruct : pointer to a SDIO_InitPara structure .
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* @retval None
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*/
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void SDIO_Init(SDIO_InitPara *SDIO_InitParaStruct)
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{
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uint32_t temp = 0;
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/* SDIO CLKCTLR Configuration */
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/* Get the SDIO CLKCTLR value */
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temp = SDIO->CLKCTLR;
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/* Clear CLKCTLR register */
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temp &= CLKCTLR_CLEAR_MASK;
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/* Configure the SDIO_ClockDiv value */
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/* Configure the SDIO_ClockPWRSave value */
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/* Configure the SDIO_ClockBypassState value */
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/* Configure the SDIO_BusMode value */
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/* Configure the SDIO_ClockEdge value */
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/* Configure the SDIO_HWFlowCtrlState value */
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temp |= (SDIO_InitParaStruct->SDIO_ClockDiv | SDIO_InitParaStruct->SDIO_ClockPWRSave |
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SDIO_InitParaStruct->SDIO_ClockBypassState | SDIO_InitParaStruct->SDIO_BusMode |
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SDIO_InitParaStruct->SDIO_ClockEdge | SDIO_InitParaStruct->SDIO_HWFlowCtrlState);
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/* Update the SDIO CLKCTLR */
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SDIO->CLKCTLR = temp;
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}
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/**
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* @brief Fill each SDIO_InitParaStruct Struct member with a default value.
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* @param SDIO_InitParaStruct: pointer to an SDIO_InitPara structure.
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* @retval None
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*/
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void SDIO_ParaInit(SDIO_InitPara *SDIO_InitParaStruct)
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{
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/* Fill the default value */
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SDIO_InitParaStruct->SDIO_ClockDiv = 0x00;
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SDIO_InitParaStruct->SDIO_ClockEdge = SDIO_CLOCKEDGE_RISING;
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SDIO_InitParaStruct->SDIO_ClockBypassState = SDIO_CLOCKBYPASSSTATE_DISABLE;
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SDIO_InitParaStruct->SDIO_ClockPWRSave = SDIO_CLOCKPWRSAVE_DISABLE;
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SDIO_InitParaStruct->SDIO_BusMode = SDIO_BUSMODE_1B;
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SDIO_InitParaStruct->SDIO_HWFlowCtrlState = SDIO_HWFLOWCTRLSTATE_DISABLE;
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}
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/**
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* @brief ENABLE or DISABLE the SDIO Clock.
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* @param NewValue: ENABLE or DISABLE.
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* @retval None
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*/
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void SDIO_Clock_Enable(TypeState NewValue)
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{
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if (NewValue != DISABLE) {
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SDIO->CLKCTLR |= SDIO_CLKCTLR_CKEN;
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} else {
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SDIO->CLKCTLR &= (uint16_t)~(SDIO_CLKCTLR_CKEN);
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}
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}
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/**
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* @brief Configure the power state of SDIO.
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* @param SDIO_PwrState: new Power state for SDIO.
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* This value will be :
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* @arg SDIO_PWRSTATE_ON
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* @arg SDIO_PWRSTATE_OFF
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* @retval None
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*/
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void SDIO_SetPWRState(uint32_t SDIO_PwrState)
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{
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/* Update the SDIO POWER */
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SDIO->POWER |= SDIO_PwrState;
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}
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/**
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* @brief Get the power state of SDIO.
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* @param None
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* @retval Power state for SDIO.
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* This value will be :
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* - 0x00: Power OFF
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* - 0x02: Power UP
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* - 0x03: Power ON
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*/
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uint32_t SDIO_GetPWRState(void)
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{
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return (SDIO->POWER & (~POWER_PWRSTATE_MASK));
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}
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/**
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* @brief Configure interrupts enables.
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* @param SDIO_INT: The interrupts sources to configure.
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* This value will be :
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* @arg SDIO_INT_CCRCFAIL: Command response CRC failed interrupt
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* @arg SDIO_INT_DTCRCFAIL: Data CRC failed interrupt
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* @arg SDIO_INT_CMDTMOUT: Command response timeout interrupt
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* @arg SDIO_INT_DTTMOUT: Data timeout interrupt
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* @arg SDIO_INT_TXURE: Transmit FIFO underrun error interrupt
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* @arg SDIO_INT_RXORE: Received FIFO overrun error interrupt
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* @arg SDIO_INT_CMDREND: Command response received (CRC check passed) interrupt
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* @arg SDIO_INT_CMDSENT: Command sent (no response required) interrupt
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* @arg SDIO_INT_DTEND: Data end (data counter, SDIDTCNT, is zero) interrupt
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* @arg SDIO_INT_STBITE: Start bit not detected on all data signals in wide bus mode interrupt
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* @arg SDIO_INT_DTBLKEND: Data block sent/received (CRC check passed) interrupt
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* @arg SDIO_INT_CMDRUN: Command transfer in progress interrupt
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* @arg SDIO_INT_TXRUN: Data transmit in progress interrupt
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* @arg SDIO_INT_RXRUN: Data receive in progress interrupt
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* @arg SDIO_INT_TXFIFOHE: Transmit FIFO Half Empty interrupt
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* @arg SDIO_INT_RXFIFOHF: Receive FIFO Half Full interrupt
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* @arg SDIO_INT_TXFIFOF: Transmit FIFO full interrupt
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* @arg SDIO_INT_RXFIFOF: Receive FIFO full interrupt
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* @arg SDIO_INT_TXFIFOE: Transmit FIFO empty interrupt
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* @arg SDIO_INT_RXFIFOE: Receive FIFO empty interrupt
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* @arg SDIO_INT_TXDTVAL: Data valid in transmit FIFO interrupt
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* @arg SDIO_INT_RXDTVAL: Data valid in receive FIFO interrupt
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* @arg SDIO_INT_SDIOINT: SD I/O interrupt received interrupt
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* @arg SDIO_INT_ATAEND: CE-ATA command completion signal received for CMD61 interrupt
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* @param NewValue: ENABLE or DISABLE.
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* @retval None
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*/
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void SDIO_INTConfig(uint32_t SDIO_INT, TypeState NewValue)
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{
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if (NewValue != DISABLE) {
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/* Enable the interrupt */
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SDIO->IER |= SDIO_INT;
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} else {
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/* Disable the interrupt */
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SDIO->IER &= ~SDIO_INT;
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}
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}
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/**
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* @brief Enable or disable the DMA request for SDIO.
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* @param NewValue: ENABLE or DISABLE.
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* @retval None
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*/
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void SDIO_DMA_Enable(TypeState NewValue)
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{
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if (NewValue != DISABLE) {
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/* Enable DMA request */
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SDIO->DTCTLR |= SDIO_DTCTLR_DMAEN;
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} else {
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/* Disenable DMA request */
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SDIO->DTCTLR &= (uint16_t)~((uint16_t)SDIO_DTCTLR_DMAEN);
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}
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}
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/**
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* @brief Initialize the SDIO Command.
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* @param SDIO_CmdInitParaStruct : pointer to a SDIO_CmdInitPara structure.
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* @retval None
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*/
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void SDIO_SendCMD(SDIO_CmdInitPara *SDIO_CmdInitParaStruct)
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{
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uint32_t temp = 0;
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/* SDIO PARA Configuration */
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/* Configure the SDIO_CMDParameter value */
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SDIO->PARA = SDIO_CmdInitParaStruct->SDIO_CMDParameter;
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/* SDIO CMD Configuration */
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/* Get the SDIO CMD value */
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temp = SDIO->CMD;
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/* Clear CMD register */
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temp &= CMD_CLEAR_MASK;
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/* Configure the SDIO_CMDIndex value */
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/* Configure the SDIO_ResponseType value */
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/* Configure the SDIO_WaitINTState value */
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/* Configure the SDIO_CSMState value */
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temp |= (uint32_t)SDIO_CmdInitParaStruct->SDIO_CMDIndex | SDIO_CmdInitParaStruct->SDIO_ResponseType
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| SDIO_CmdInitParaStruct->SDIO_WaitINTState | SDIO_CmdInitParaStruct->SDIO_CSMState;
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/* Update the SDIO CMD */
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SDIO->CMD = temp;
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}
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/**
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* @brief Fill SDIO_CmdInitStruct member with a default value.
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* @param SDIO_CmdInitParaStruct: pointer to an SDIO_CmdInitPara structure.
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* @retval None
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*/
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void SDIO_CMDParaInit(SDIO_CmdInitPara *SDIO_CmdInitParaStruct)
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{
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/* Fill the default value */
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SDIO_CmdInitParaStruct->SDIO_CMDParameter = 0x00;
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SDIO_CmdInitParaStruct->SDIO_CMDIndex = 0x00;
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SDIO_CmdInitParaStruct->SDIO_ResponseType = SDIO_RESPONSETYPE_NO ;
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SDIO_CmdInitParaStruct->SDIO_WaitINTState = SDIO_WAITINTSTATE_NO;
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SDIO_CmdInitParaStruct->SDIO_CSMState = SDIO_CSMSTATE_DISABLE;
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}
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/**
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* @brief Return last response command index.
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* @param None
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* @retval Return last response command index.
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*/
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uint8_t SDIO_GetCMDResponse(void)
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{
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return (uint8_t)(SDIO->RESPCMD);
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}
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/**
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* @brief Return the response for the last received command.
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* @param SDIO_RESP: The SDIO response registers.
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* This value will be :
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* @arg SDIO_RESP1: Response Register 1
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* @arg SDIO_RESP2: Response Register 2
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* @arg SDIO_RESP3: Response Register 3
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* @arg SDIO_RESP4: Response Register 4
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* @retval The Corresponding response register value.
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*/
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uint32_t SDIO_GetResponse(uint32_t SDIO_RESP)
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{
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__IO uint32_t temp = 0;
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temp = SDIO_RESP_ADDR + SDIO_RESP;
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return (*(__IO uint32_t *) temp);
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}
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/**
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* @brief Initialize the SDIO SDIO_DataInitParaStruct members.
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* @param SDIO_DataInitParaStruct : pointer to a SDIO_DataInitPara structure.
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* @retval None
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*/
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void SDIO_DataConfig(SDIO_DataInitPara *SDIO_DataInitParaStruct)
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{
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uint32_t temp = 0;
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/* SDIO DTTR Configuration */
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/* Set the SDIO SDIO_DataTimeOut value */
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SDIO->DTTR = SDIO_DataInitParaStruct->SDIO_DataTimeOut;
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/* SDIO DTLEN Configuration */
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/* Set the SDIO SDIO_DataLength value */
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SDIO->DTLEN = SDIO_DataInitParaStruct->SDIO_DataLength;
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/* SDIO DTCTLR Configuration */
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/* Get the SDIO DTCTLR value */
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temp = SDIO->DTCTLR;
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/* Clear DTCTLR register */
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temp &= DTCTLR_CLEAR_MASK;
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/* Configure the SDIO_DataBlockSize value */
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/* Configure the SDIO_TransDirection value */
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/* Configure the SDIO_TransMode value */
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/* Configure the SDIO_DSMState value */
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temp |= (uint32_t)SDIO_DataInitParaStruct->SDIO_DataBlockSize | SDIO_DataInitParaStruct->SDIO_TransDirection
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| SDIO_DataInitParaStruct->SDIO_TransMode | SDIO_DataInitParaStruct->SDIO_DSMState;
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/* Update the SDIO DTCTLR */
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SDIO->DTCTLR = temp;
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}
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/**
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* @brief Fill each SDIO_DataInitParaStruct member with a default value.
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* @param SDIO_DataInitParaStruct: pointer to an SDIO_DataInitPara structure.
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* @retval None
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*/
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void SDIO_DataParaInit(SDIO_DataInitPara *SDIO_DataInitParaStruct)
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{
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/* Fill the default value */
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SDIO_DataInitParaStruct->SDIO_DataTimeOut = 0xFFFFFFFF;
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SDIO_DataInitParaStruct->SDIO_DataLength = 0x00;
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SDIO_DataInitParaStruct->SDIO_DataBlockSize = SDIO_DATABLOCKSIZE_1B;
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SDIO_DataInitParaStruct->SDIO_TransDirection = SDIO_TRANSDIRECTION_TOCARD;
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SDIO_DataInitParaStruct->SDIO_TransMode = SDIO_TRANSMODE_BLOCK;
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SDIO_DataInitParaStruct->SDIO_DSMState = SDIO_DSMSTATE_DISABLE;
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}
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/**
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* @brief Return the number of remaining data bytes to be transferred to card.
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* @param None
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* @retval Number of remaining data bytes to be transferred
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*/
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uint32_t SDIO_GetDataCount(void)
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{
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return SDIO->DTCNT;
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}
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/**
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* @brief Read one word from receive FIFO.
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* @param None
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* @retval Data received
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*/
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uint32_t SDIO_ReadData(void)
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{
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return SDIO->FIFO;
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}
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/**
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* @brief Write one word to transmit FIFO.
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* @param Data: 32-bit data write to the card.
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* @retval None
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*/
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void SDIO_WriteData(uint32_t Data)
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||
|
|
{
|
||
|
|
SDIO->FIFO = Data;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Return the number of words remaining to be written or read from FIFO.
|
||
|
|
* @param None
|
||
|
|
* @retval Remaining number of words.
|
||
|
|
*/
|
||
|
|
uint32_t SDIO_GetFIFOCount(void)
|
||
|
|
{
|
||
|
|
return SDIO->FIFOCNT;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Start SD I/O Read Wait operation.
|
||
|
|
* @param NewValue: ENABLE or DISABLE.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void SDIO_StartSDIOReadWait(TypeState NewValue)
|
||
|
|
{
|
||
|
|
if (NewValue != DISABLE) {
|
||
|
|
/* Start Read Wait operation */
|
||
|
|
SDIO->DTCTLR |= SDIO_DTCTLR_RWSTART;
|
||
|
|
} else {
|
||
|
|
SDIO->DTCTLR &= (uint16_t)~((uint16_t)SDIO_DTCTLR_RWSTART);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Stop the SD I/O Read Wait operation.
|
||
|
|
* @param NewValue: ENABLE or DISABLE.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void SDIO_StopSDIOReadWait(TypeState NewValue)
|
||
|
|
{
|
||
|
|
if (NewValue != DISABLE) {
|
||
|
|
SDIO->DTCTLR |= SDIO_DTCTLR_RWSTOP;
|
||
|
|
} else {
|
||
|
|
/* Stop Read Wait operation */
|
||
|
|
SDIO->DTCTLR &= (uint16_t)~((uint16_t)SDIO_DTCTLR_RWSTOP);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Configure the SD I/O read wait mode.
|
||
|
|
* @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode.
|
||
|
|
* This value will be :
|
||
|
|
* @arg SDIO_READWAITMODE_CLK: Read Wait operation realize by stopping SDIOCLK
|
||
|
|
* @arg SDIO_READWAITMODE_DAT2: Read Wait operation use SDIO_DAT2
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)
|
||
|
|
{
|
||
|
|
if (SDIO_ReadWaitMode == SDIO_READWAITMODE_CLK) {
|
||
|
|
/* Read Wait operation stop SDIOCLK */
|
||
|
|
SDIO->DTCTLR |= SDIO_DTCTLR_RWMODE;
|
||
|
|
} else {
|
||
|
|
/* Read Wait operation use SDIO_DAT2 */
|
||
|
|
SDIO->DTCTLR &= (uint16_t)~((uint16_t)SDIO_DTCTLR_RWMODE);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief SD I/O Mode Operation configuration.
|
||
|
|
* @param NewValue: ENABLE or DISABLE.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void SDIO_SetSDIOOperation(TypeState NewValue)
|
||
|
|
{
|
||
|
|
if (NewValue != DISABLE) {
|
||
|
|
/* Enable I/O Mode Operation */
|
||
|
|
SDIO->DTCTLR |= SDIO_DTCTLR_SDIOEN;
|
||
|
|
} else {
|
||
|
|
/* Disenable I/O Mode Operation */
|
||
|
|
SDIO->DTCTLR &= (uint16_t)~((uint16_t)SDIO_DTCTLR_SDIOEN);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Enable or disable the SD I/O suspend operation.
|
||
|
|
* @param NewValue: ENABLE or DISABLE.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void SDIO_SendSDIOSuspend_Enable(TypeState NewValue)
|
||
|
|
{
|
||
|
|
if (NewValue != DISABLE) {
|
||
|
|
/* Enable suspend operation */
|
||
|
|
SDIO->CMD |= SDIO_CMD_SDIOSUSPEND;
|
||
|
|
} else {
|
||
|
|
/* Disenable suspend operation */
|
||
|
|
SDIO->CMD &= (uint16_t)~((uint16_t)SDIO_CMD_SDIOSUSPEND);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Enable or disable the CE-ATA command completion signal.
|
||
|
|
* @param NewValue: ENABLE or DISABLE.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void SDIO_CMDCompletion_Enable(TypeState NewValue)
|
||
|
|
{
|
||
|
|
if (NewValue != DISABLE) {
|
||
|
|
/* Enable CE-ATA command completion signal */
|
||
|
|
SDIO->CMD |= SDIO_CMD_ENCMDC;
|
||
|
|
} else {
|
||
|
|
/* Disenable CE-ATA command completion signal */
|
||
|
|
SDIO->CMD &= (uint16_t)~((uint16_t)SDIO_CMD_ENCMDC);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Enable or disable the CE-ATA interrupt.
|
||
|
|
* @param NewValue: ENABLE or DISABLE.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void SDIO_CEATAInt_Enable(TypeState NewValue)
|
||
|
|
{
|
||
|
|
if (NewValue != ENABLE) {
|
||
|
|
/* Enable CE-ATA interrupt */
|
||
|
|
SDIO->CMD |= SDIO_CMD_NIEN;
|
||
|
|
} else {
|
||
|
|
/* Disenable CE-ATA interrupt */
|
||
|
|
SDIO->CMD &= (uint16_t)~((uint16_t)SDIO_CMD_NIEN);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Send CE-ATA command (CMD61).
|
||
|
|
* @param NewValue: ENABLE or DISABLE.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void SDIO_SendCEATA_Enable(TypeState NewValue)
|
||
|
|
{
|
||
|
|
if (NewValue != DISABLE) {
|
||
|
|
SDIO->CMD |= SDIO_CMD_ATACMD;
|
||
|
|
} else {
|
||
|
|
SDIO->CMD &= (uint16_t)~((uint16_t)SDIO_CMD_ATACMD);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Check whether the flag is set or not.
|
||
|
|
* @param SDIO_FLAG: the flag to check.
|
||
|
|
* This value will be :
|
||
|
|
* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC failed)
|
||
|
|
* @arg SDIO_FLAG_DTCRCFAIL: Data block sent/received (CRC failed)
|
||
|
|
* @arg SDIO_FLAG_CMDTMOUT: Command response timeout
|
||
|
|
* @arg SDIO_FLAG_DTTMOUT: Data timeout
|
||
|
|
* @arg SDIO_FLAG_TXURE: Transmit FIFO underrun error
|
||
|
|
* @arg SDIO_FLAG_RXORE: Received FIFO overrun error
|
||
|
|
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
|
||
|
|
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
|
||
|
|
* @arg SDIO_FLAG_DTEND: Data end (data counter, SDIDTCNT, is zero)
|
||
|
|
* @arg SDIO_FLAG_STBITE: Start bit not detected on all data signals in wide
|
||
|
|
* bus mode.
|
||
|
|
* @arg SDIO_FLAG_DTBLKEND: Data block sent/received (CRC check passed)
|
||
|
|
* @arg SDIO_FLAG_CMDRUN: Command transfer in progress
|
||
|
|
* @arg SDIO_FLAG_TXRUN: Data transmit in progress
|
||
|
|
* @arg SDIO_FLAG_RXRUN: Data receive in progress
|
||
|
|
* @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
|
||
|
|
* @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
|
||
|
|
* @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
|
||
|
|
* @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
|
||
|
|
* @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
|
||
|
|
* @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
|
||
|
|
* @arg SDIO_FLAG_TXDTVAL: Data available in transmit FIFO
|
||
|
|
* @arg SDIO_FLAG_RXDTVAL: Data available in receive FIFO
|
||
|
|
* @arg SDIO_FLAG_SDIOINT: SD I/O interrupt received
|
||
|
|
* @arg SDIO_FLAG_ATAEND: CE-ATA command completion signal received for CMD61
|
||
|
|
* @retval The new state of SDIO_FLAG (SET or RESET).
|
||
|
|
*/
|
||
|
|
TypeState SDIO_GetBitState(uint32_t SDIO_FLAG)
|
||
|
|
{
|
||
|
|
if ((SDIO->STR & SDIO_FLAG) != (uint32_t)RESET) {
|
||
|
|
return SET;
|
||
|
|
} else {
|
||
|
|
return RESET;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Clear the pending flags.
|
||
|
|
* @param SDIO_FLAG: the flag to clear.
|
||
|
|
* This value will be :
|
||
|
|
* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
|
||
|
|
* @arg SDIO_FLAG_DTCRCFAIL: Data block sent/received (CRC check failed)
|
||
|
|
* @arg SDIO_FLAG_CMDTMOUT: Command response timeout
|
||
|
|
* @arg SDIO_FLAG_DTTMOUT: Data timeout
|
||
|
|
* @arg SDIO_FLAG_TXURE: Transmit FIFO underrun error
|
||
|
|
* @arg SDIO_FLAG_RXORE: Received FIFO overrun error
|
||
|
|
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
|
||
|
|
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
|
||
|
|
* @arg SDIO_FLAG_DTEND: Data end (data counter, SDIO_DTCNT, is zero)
|
||
|
|
* @arg SDIO_FLAG_STBITE: Start bit not detected on all data signals in wide bus mode
|
||
|
|
* @arg SDIO_FLAG_DTBLKEND: Data block sent/received (CRC check passed)
|
||
|
|
* @arg SDIO_FLAG_SDIOINT: SD I/O interrupt received
|
||
|
|
* @arg SDIO_FLAG_ATAEND: CE-ATA command completion signal received for CMD61
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void SDIO_ClearBitState(uint32_t SDIO_FLAG)
|
||
|
|
{
|
||
|
|
SDIO->ICR = SDIO_FLAG;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Check whether the interrupt is pending or not.
|
||
|
|
* @param SDIO_INT: the SDIO interrupt source to check.
|
||
|
|
* This value will be :
|
||
|
|
* @arg SDIO_INT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
||
|
|
* @arg SDIO_INT_DTCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
||
|
|
* @arg SDIO_INT_CMDTMOUT: Command response timeout interrupt
|
||
|
|
* @arg SDIO_INT_DTTMOUT: Data timeout interrupt
|
||
|
|
* @arg SDIO_INT_TXURE: Transmit FIFO underrun error interrupt
|
||
|
|
* @arg SDIO_INT_RXORE: Received FIFO overrun error interrupt
|
||
|
|
* @arg SDIO_INT_CMDREND: Command response received (CRC check passed) interrupt
|
||
|
|
* @arg SDIO_INT_CMDSENT: Command sent (no response required) interrupt
|
||
|
|
* @arg SDIO_INT_DTEND: Data end (data counter, SDIDTCNT, is zero) interrupt
|
||
|
|
* @arg SDIO_INT_STBITE: Start bit not detected on all data signals in wide bus mode interrupt
|
||
|
|
* @arg SDIO_INT_DTBLKEND: Data block sent/received (CRC check passed) interrupt
|
||
|
|
* @arg SDIO_INT_CMDRUN: Command transfer in progress interrupt
|
||
|
|
* @arg SDIO_INT_TXRUN: Data transmit in progress interrupt
|
||
|
|
* @arg SDIO_INT_RXRUN: Data receive in progress interrupt
|
||
|
|
* @arg SDIO_INT_TXFIFOHE: Transmit FIFO Half Empty interrupt
|
||
|
|
* @arg SDIO_INT_RXFIFOHF: Receive FIFO Half Full interrupt
|
||
|
|
* @arg SDIO_INT_TXFIFOF: Transmit FIFO full interrupt
|
||
|
|
* @arg SDIO_INT_RXFIFOF: Receive FIFO full interrupt
|
||
|
|
* @arg SDIO_INT_TXFIFOE: Transmit FIFO empty interrupt
|
||
|
|
* @arg SDIO_INT_RXFIFOE: Receive FIFO empty interrupt
|
||
|
|
* @arg SDIO_INT_TXDTVAL: Data available in transmit FIFO interrupt
|
||
|
|
* @arg SDIO_INT_RXDTVAL: Data available in receive FIFO interrupt
|
||
|
|
* @arg SDIO_INT_SDIOINT: SD I/O interrupt received interrupt
|
||
|
|
* @arg SDIO_INT_ATAEND: CE-ATA command completion signal received for CMD61 interrupt
|
||
|
|
* @retval The new state of SDIO_INT (SET or RESET).
|
||
|
|
*/
|
||
|
|
TypeState SDIO_GetIntBitState(uint32_t SDIO_INT)
|
||
|
|
{
|
||
|
|
if ((SDIO->STR & SDIO_INT) != (uint32_t)RESET) {
|
||
|
|
return SET;
|
||
|
|
} else {
|
||
|
|
return RESET;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Clear the interrupt pending bits.
|
||
|
|
* @param SDIO_INT: the interrupt pending bit to clear.
|
||
|
|
* This value will be :
|
||
|
|
* @arg SDIO_INT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
||
|
|
* @arg SDIO_INT_DTCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
||
|
|
* @arg SDIO_INT_CMDTMOUT: Command response timeout interrupt
|
||
|
|
* @arg SDIO_INT_DTTMOUT: Data timeout interrupt
|
||
|
|
* @arg SDIO_INT_TXURE: Transmit FIFO underrun error interrupt
|
||
|
|
* @arg SDIO_INT_RXORE: Received FIFO overrun error interrupt
|
||
|
|
* @arg SDIO_INT_CMDREND: Command response received (CRC check passed) interrupt
|
||
|
|
* @arg SDIO_INT_CMDSENT: Command sent (no response required) interrupt
|
||
|
|
* @arg SDIO_INT_DTEND: Data end (data counter, SDIDTCNT, is zero) interrupt
|
||
|
|
* @arg SDIO_INT_STBITE: Start bit not detected on all data signals in wide
|
||
|
|
* bus mode interrupt
|
||
|
|
* @arg SDIO_INT_SDIOINT: SD I/O interrupt received interrupt
|
||
|
|
* @arg SDIO_INT_ATAEND: CE-ATA command completion signal received for CMD61
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void SDIO_ClearIntBitState(uint32_t SDIO_INT)
|
||
|
|
{
|
||
|
|
SDIO->ICR = SDIO_INT;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
#endif
|