2018-11-29 17:00:22 +08:00
|
|
|
/*
|
2021-03-08 22:40:39 +08:00
|
|
|
* Copyright (c) 2006-2021, RT-Thread Development Team
|
2018-11-29 17:00:22 +08:00
|
|
|
*
|
|
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
|
|
*
|
|
|
|
* Change Logs:
|
|
|
|
* Date Author Notes
|
2019-01-08 11:58:57 +08:00
|
|
|
* 2018-11-10 SummerGift first version
|
2020-10-14 15:02:23 +08:00
|
|
|
* 2020-10-14 Dozingfiretruck Porting for stm32wbxx
|
2018-11-29 17:00:22 +08:00
|
|
|
*/
|
|
|
|
|
|
|
|
#ifndef __DRV_DMA_H_
|
|
|
|
#define __DRV_DMA_H_
|
|
|
|
|
|
|
|
#include <rtthread.h>
|
2019-01-22 09:14:06 +08:00
|
|
|
#include <board.h>
|
2018-11-29 17:00:22 +08:00
|
|
|
|
2019-01-09 10:10:39 +08:00
|
|
|
#ifdef __cplusplus
|
|
|
|
extern "C" {
|
|
|
|
#endif
|
|
|
|
|
2021-11-01 14:56:23 +08:00
|
|
|
#if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32L5)\
|
2021-11-15 10:26:14 +08:00
|
|
|
|| defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G0) \
|
|
|
|
|| defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)|| defined(SOC_SERIES_STM32F3) \
|
|
|
|
|| defined(SOC_SERIES_STM32U5)
|
2018-11-29 17:00:22 +08:00
|
|
|
#define DMA_INSTANCE_TYPE DMA_Channel_TypeDef
|
2019-06-18 15:54:36 +08:00
|
|
|
#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)\
|
2021-11-15 13:43:33 +08:00
|
|
|
|| defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
|
2018-11-29 17:00:22 +08:00
|
|
|
#define DMA_INSTANCE_TYPE DMA_Stream_TypeDef
|
2021-01-29 10:28:18 +08:00
|
|
|
#endif /* defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) */
|
2018-11-29 17:00:22 +08:00
|
|
|
|
|
|
|
struct dma_config {
|
|
|
|
DMA_INSTANCE_TYPE *Instance;
|
|
|
|
rt_uint32_t dma_rcc;
|
|
|
|
IRQn_Type dma_irq;
|
|
|
|
|
2021-08-05 16:00:35 +08:00
|
|
|
#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)|| defined(SOC_SERIES_STM32F3)
|
2018-11-29 17:00:22 +08:00
|
|
|
rt_uint32_t channel;
|
|
|
|
#endif
|
|
|
|
|
2021-01-29 10:28:18 +08:00
|
|
|
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4)\
|
2021-11-01 14:56:23 +08:00
|
|
|
|| defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32L5)
|
2018-11-29 17:00:22 +08:00
|
|
|
rt_uint32_t request;
|
|
|
|
#endif
|
|
|
|
};
|
|
|
|
|
2019-01-09 10:10:39 +08:00
|
|
|
#ifdef __cplusplus
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2018-11-29 17:00:22 +08:00
|
|
|
#endif /*__DRV_DMA_H_ */
|