196 lines
6.3 KiB
C
196 lines
6.3 KiB
C
|
/*
|
||
|
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||
|
* Copyright 2016-2017 NXP
|
||
|
*
|
||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||
|
* are permitted provided that the following conditions are met:
|
||
|
*
|
||
|
* o Redistributions of source code must retain the above copyright notice, this list
|
||
|
* of conditions and the following disclaimer.
|
||
|
*
|
||
|
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||
|
* list of conditions and the following disclaimer in the documentation and/or
|
||
|
* other materials provided with the distribution.
|
||
|
*
|
||
|
* o Neither the name of the copyright holder nor the names of its
|
||
|
* contributors may be used to endorse or promote products derived from this
|
||
|
* software without specific prior written permission.
|
||
|
*
|
||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||
|
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||
|
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||
|
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||
|
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||
|
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||
|
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||
|
*/
|
||
|
|
||
|
#include "fsl_gpio.h"
|
||
|
|
||
|
/*******************************************************************************
|
||
|
* Variables
|
||
|
******************************************************************************/
|
||
|
static PORT_Type *const s_portBases[] = PORT_BASE_PTRS;
|
||
|
static GPIO_Type *const s_gpioBases[] = GPIO_BASE_PTRS;
|
||
|
|
||
|
/*******************************************************************************
|
||
|
* Prototypes
|
||
|
******************************************************************************/
|
||
|
|
||
|
/*!
|
||
|
* @brief Gets the GPIO instance according to the GPIO base
|
||
|
*
|
||
|
* @param base GPIO peripheral base pointer(PTA, PTB, PTC, etc.)
|
||
|
* @retval GPIO instance
|
||
|
*/
|
||
|
static uint32_t GPIO_GetInstance(GPIO_Type *base);
|
||
|
|
||
|
/*******************************************************************************
|
||
|
* Code
|
||
|
******************************************************************************/
|
||
|
|
||
|
static uint32_t GPIO_GetInstance(GPIO_Type *base)
|
||
|
{
|
||
|
uint32_t instance;
|
||
|
|
||
|
/* Find the instance index from base address mappings. */
|
||
|
for (instance = 0; instance < ARRAY_SIZE(s_gpioBases); instance++)
|
||
|
{
|
||
|
if (s_gpioBases[instance] == base)
|
||
|
{
|
||
|
break;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
assert(instance < ARRAY_SIZE(s_gpioBases));
|
||
|
|
||
|
return instance;
|
||
|
}
|
||
|
|
||
|
void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config)
|
||
|
{
|
||
|
assert(config);
|
||
|
|
||
|
if (config->pinDirection == kGPIO_DigitalInput)
|
||
|
{
|
||
|
base->PDDR &= ~(1U << pin);
|
||
|
}
|
||
|
else
|
||
|
{
|
||
|
GPIO_WritePinOutput(base, pin, config->outputLogic);
|
||
|
base->PDDR |= (1U << pin);
|
||
|
}
|
||
|
}
|
||
|
|
||
|
uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type *base)
|
||
|
{
|
||
|
uint8_t instance;
|
||
|
PORT_Type *portBase;
|
||
|
instance = GPIO_GetInstance(base);
|
||
|
portBase = s_portBases[instance];
|
||
|
return portBase->ISFR;
|
||
|
}
|
||
|
|
||
|
void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask)
|
||
|
{
|
||
|
uint8_t instance;
|
||
|
PORT_Type *portBase;
|
||
|
instance = GPIO_GetInstance(base);
|
||
|
portBase = s_portBases[instance];
|
||
|
portBase->ISFR = mask;
|
||
|
}
|
||
|
|
||
|
#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER
|
||
|
void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribute)
|
||
|
{
|
||
|
base->GACR = ((uint32_t)attribute << GPIO_GACR_ACB0_SHIFT) | ((uint32_t)attribute << GPIO_GACR_ACB1_SHIFT) |
|
||
|
((uint32_t)attribute << GPIO_GACR_ACB2_SHIFT) | ((uint32_t)attribute << GPIO_GACR_ACB3_SHIFT);
|
||
|
}
|
||
|
#endif
|
||
|
|
||
|
#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT
|
||
|
|
||
|
/*******************************************************************************
|
||
|
* Variables
|
||
|
******************************************************************************/
|
||
|
static FGPIO_Type *const s_fgpioBases[] = FGPIO_BASE_PTRS;
|
||
|
|
||
|
/*******************************************************************************
|
||
|
* Prototypes
|
||
|
******************************************************************************/
|
||
|
/*!
|
||
|
* @brief Gets the FGPIO instance according to the GPIO base
|
||
|
*
|
||
|
* @param base FGPIO peripheral base pointer(PTA, PTB, PTC, etc.)
|
||
|
* @retval FGPIO instance
|
||
|
*/
|
||
|
static uint32_t FGPIO_GetInstance(FGPIO_Type *base);
|
||
|
|
||
|
/*******************************************************************************
|
||
|
* Code
|
||
|
******************************************************************************/
|
||
|
|
||
|
static uint32_t FGPIO_GetInstance(FGPIO_Type *base)
|
||
|
{
|
||
|
uint32_t instance;
|
||
|
|
||
|
/* Find the instance index from base address mappings. */
|
||
|
for (instance = 0; instance < ARRAY_SIZE(s_fgpioBases); instance++)
|
||
|
{
|
||
|
if (s_fgpioBases[instance] == base)
|
||
|
{
|
||
|
break;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
assert(instance < ARRAY_SIZE(s_fgpioBases));
|
||
|
|
||
|
return instance;
|
||
|
}
|
||
|
|
||
|
void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config)
|
||
|
{
|
||
|
assert(config);
|
||
|
|
||
|
if (config->pinDirection == kGPIO_DigitalInput)
|
||
|
{
|
||
|
base->PDDR &= ~(1U << pin);
|
||
|
}
|
||
|
else
|
||
|
{
|
||
|
FGPIO_WritePinOutput(base, pin, config->outputLogic);
|
||
|
base->PDDR |= (1U << pin);
|
||
|
}
|
||
|
}
|
||
|
|
||
|
uint32_t FGPIO_GetPinsInterruptFlags(FGPIO_Type *base)
|
||
|
{
|
||
|
uint8_t instance;
|
||
|
instance = FGPIO_GetInstance(base);
|
||
|
PORT_Type *portBase;
|
||
|
portBase = s_portBases[instance];
|
||
|
return portBase->ISFR;
|
||
|
}
|
||
|
|
||
|
void FGPIO_ClearPinsInterruptFlags(FGPIO_Type *base, uint32_t mask)
|
||
|
{
|
||
|
uint8_t instance;
|
||
|
instance = FGPIO_GetInstance(base);
|
||
|
PORT_Type *portBase;
|
||
|
portBase = s_portBases[instance];
|
||
|
portBase->ISFR = mask;
|
||
|
}
|
||
|
|
||
|
#if defined(FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER
|
||
|
void FGPIO_CheckAttributeBytes(FGPIO_Type *base, gpio_checker_attribute_t attribute)
|
||
|
{
|
||
|
base->GACR = (attribute << FGPIO_GACR_ACB0_SHIFT) | (attribute << FGPIO_GACR_ACB1_SHIFT) |
|
||
|
(attribute << FGPIO_GACR_ACB2_SHIFT) | (attribute << FGPIO_GACR_ACB3_SHIFT);
|
||
|
}
|
||
|
#endif
|
||
|
|
||
|
#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */
|