76 lines
2.7 KiB
C
76 lines
2.7 KiB
C
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/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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* Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2024-02-20 CDT first version
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*/
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#ifndef __QSPI_CONFIG_H__
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#define __QSPI_CONFIG_H__
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#include <rtthread.h>
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#include "irq_config.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef BSP_USING_QSPI
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#ifndef QSPI_BUS_CONFIG
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#define QSPI_BUS_CONFIG \
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{ \
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.Instance = CM_QSPI, \
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.clock = FCG1_PERIPH_QSPI, \
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.timeout = 5000UL, \
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.err_irq.irq_config = \
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{ \
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.irq_num = BSP_QSPI_ERR_IRQ_NUM, \
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.irq_prio = BSP_QSPI_ERR_IRQ_PRIO, \
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.int_src = INT_SRC_QSPI_INTR, \
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}, \
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}
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#endif /* QSPI_BUS_CONFIG */
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#ifndef QSPI_INIT_PARAMS
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#define QSPI_INIT_PARAMS \
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{ \
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.u32PrefetchMode = QSPI_PREFETCH_MD_INVD, \
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.u32SetupTime = QSPI_QSSN_SETUP_ADVANCE_QSCK0P5, \
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.u32ReleaseTime = QSPI_QSSN_RELEASE_DELAY_QSCK32, \
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.u32IntervalTime = QSPI_QSSN_INTERVAL_QSCK1, \
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}
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#endif /* QSPI_INIT_PARAMS */
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#define QSPI_WP_PIN_LEVEL QSPI_WP_PIN_HIGH
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#ifdef BSP_QSPI_USING_DMA
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#ifndef QSPI_DMA_CONFIG
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#define QSPI_DMA_CONFIG \
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{ \
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.Instance = QSPI_DMA_INSTANCE, \
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.channel = QSPI_DMA_CHANNEL, \
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.clock = QSPI_DMA_CLOCK, \
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.trigger_select = QSPI_DMA_TRIG_SELECT, \
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.trigger_event = EVT_SRC_AOS_STRG, \
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.flag = QSPI_DMA_TRANS_FLAG, \
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.irq_config = \
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{ \
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.irq_num = QSPI_DMA_IRQn, \
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.irq_prio = QSPI_DMA_INT_PRIO, \
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.int_src = QSPI_DMA_INT_SRC, \
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} \
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}
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#endif /* QSPI_DMA_CONFIG */
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#endif /* BSP_QSPI_USING_DMA */
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#endif /* BSP_USING_SPI1 */
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#ifdef __cplusplus
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}
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#endif
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#endif /*__QSPI_CONFIG_H__ */
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