2020-07-01 23:44:57 +08:00
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/*
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2021-03-21 22:23:24 +08:00
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* Copyright (c) 2006-2021, RT-Thread Development Team
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2020-07-01 23:44:57 +08:00
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-06-27 AHTYDHD the first version
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*/
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2020-06-24 19:54:42 +08:00
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#include "drv_pwm.h"
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#include <stdint.h>
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#include <stdbool.h>
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2020-07-01 23:44:57 +08:00
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#include "inc/hw_memmap.h"
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#include "driverlib/pwm.h"
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#include "driverlib/sysctl.h"
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2020-06-24 19:54:42 +08:00
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#ifdef RT_USING_PWM
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#include "pwm_config.h"
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#include "tm4c123_config.h"
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2020-07-01 23:44:57 +08:00
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#include <string.h>
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2020-06-24 19:54:42 +08:00
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#define LOG_TAG "drv.pwm"
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#include <drv_log.h>
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enum
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{
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#ifdef BSP_USING_PWM0
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PWM0_INDEX,
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#endif
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#ifdef BSP_USING_PWM1
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PWM1_INDEX,
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#endif
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#ifdef BSP_USING_PWM2
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PWM2_INDEX,
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#endif
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#ifdef BSP_USING_PWM3
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PWM3_INDEX,
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#endif
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#ifdef BSP_USING_PWM4
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PWM4_INDEX,
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#endif
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#ifdef BSP_USING_PWM5
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PWM5_INDEX,
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#endif
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#ifdef BSP_USING_PWM6
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PWM6_INDEX,
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#endif
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#ifdef BSP_USING_PWM7
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PWM7_INDEX,
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#endif
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};
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static struct tm4c123_pwm_config pwm_config[] =
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{
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#ifdef BSP_USING_PWM0
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PWM0_CONFIG,
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#endif
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#ifdef BSP_USING_PWM1
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PWM1_CONFIG,
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#endif
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#ifdef BSP_USING_PWM2
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PWM2_CONFIG,
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#endif
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#ifdef BSP_USING_PWM3
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PWM3_CONFIG,
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#endif
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#ifdef BSP_USING_PWM4
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PWM4_CONFIG,
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#endif
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#ifdef BSP_USING_PWM5
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PWM5_CONFIG,
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#endif
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#ifdef BSP_USING_PWM6
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PWM6_CONFIG,
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#endif
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#ifdef BSP_USING_PWM7
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PWM7_CONFIG,
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#endif
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};
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static struct tm4c123_pwm pwm_obj[sizeof(pwm_config) / sizeof(pwm_config[0])] = {0};
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static rt_err_t tm4c123_pwm_control(struct rt_device_pwm *device, int cmd, void *arg);
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static struct rt_pwm_ops drv_ops =
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{
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tm4c123_pwm_control
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};
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2020-07-01 23:44:57 +08:00
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static rt_err_t drv_pwm_enable(char *name, struct rt_pwm_configuration *configuration, rt_bool_t enable)
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2020-06-24 19:54:42 +08:00
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{
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2020-07-01 23:44:57 +08:00
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int num = name[3] - 0x30;
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2020-06-24 19:54:42 +08:00
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if (!enable)
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{
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2020-07-01 23:44:57 +08:00
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if (num <= 3)
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{
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/* Converts the channel number to the channel number of Hal library */
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PWMOutputState(PWM0_BASE, PWM_OUT_0_BIT << (num * 2 + (configuration->channel - 1)), false);
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}
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2020-06-24 19:54:42 +08:00
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else
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2020-07-01 23:44:57 +08:00
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{
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PWMOutputState(PWM1_BASE, PWM_OUT_0_BIT << ((num % 4) * 2 + (configuration->channel - 1)), false);
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}
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2020-06-24 19:54:42 +08:00
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}
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else
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{
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2020-07-01 23:44:57 +08:00
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if (num <= 3)
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{
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PWMOutputState(PWM0_BASE, PWM_OUT_0_BIT << (num * 2 + (configuration->channel - 1)), true);
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}
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2020-06-24 19:54:42 +08:00
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else
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2020-07-01 23:44:57 +08:00
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{
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PWMOutputState(PWM1_BASE, PWM_OUT_0_BIT << ((num % 4) * 2 + (configuration->channel - 1)), true);
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}
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2020-06-24 19:54:42 +08:00
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}
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return RT_EOK;
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}
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2020-07-01 23:44:57 +08:00
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static rt_err_t drv_pwm_get(char *name, struct rt_pwm_configuration *configuration)
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2020-06-24 19:54:42 +08:00
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{
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2020-07-01 23:44:57 +08:00
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switch (name[3])
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{
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case '0':
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configuration->period = PWMGenPeriodGet(PWM0_BASE, PWM_GEN_0);
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configuration->pulse = PWMPulseWidthGet(PWM0_BASE, PWM_OUT_0 + (uint32_t)(configuration->channel - 1));
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break;
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case '1':
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configuration->period = PWMGenPeriodGet(PWM0_BASE, PWM_GEN_1);
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configuration->pulse = PWMPulseWidthGet(PWM0_BASE, PWM_OUT_2 + (uint32_t)(configuration->channel - 1));
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break;
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case '2':
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configuration->period = PWMGenPeriodGet(PWM0_BASE, PWM_GEN_2);
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configuration->pulse = PWMPulseWidthGet(PWM0_BASE, PWM_OUT_4 + (uint32_t)(configuration->channel - 1));
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break;
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case '3':
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configuration->period = PWMGenPeriodGet(PWM0_BASE, PWM_GEN_3);
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configuration->pulse = PWMPulseWidthGet(PWM0_BASE, PWM_OUT_6 + (uint32_t)(configuration->channel - 1));
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break;
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case '4':
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configuration->period = PWMGenPeriodGet(PWM1_BASE, PWM_GEN_0);
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configuration->pulse = PWMPulseWidthGet(PWM1_BASE, PWM_OUT_0 + (uint32_t)(configuration->channel - 1));
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break;
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case '5':
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configuration->period = PWMGenPeriodGet(PWM1_BASE, PWM_GEN_1);
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configuration->pulse = PWMPulseWidthGet(PWM1_BASE, PWM_OUT_2 + (uint32_t)(configuration->channel - 1));
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break;
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case '6':
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configuration->period = PWMGenPeriodGet(PWM1_BASE, PWM_GEN_2);
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configuration->pulse = PWMPulseWidthGet(PWM1_BASE, PWM_OUT_4 + (uint32_t)(configuration->channel - 1));
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break;
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case '7':
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configuration->period = PWMGenPeriodGet(PWM1_BASE, PWM_GEN_3);
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configuration->pulse = PWMPulseWidthGet(PWM1_BASE, PWM_OUT_6 + (uint32_t)(configuration->channel - 1));
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break;
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default:
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break;
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}
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return RT_EOK;
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2020-06-24 19:54:42 +08:00
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}
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static rt_err_t drv_pwm_set(char *name, struct rt_pwm_configuration *configuration)
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{
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2020-07-01 23:44:57 +08:00
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uint32_t sysPwmClock = SysCtlPWMClockGet();
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switch (name[3])
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{
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case '0':
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PWMGenPeriodSet(PWM0_BASE, PWM_GEN_0, configuration->period / 1000 * (sysPwmClock / 1000000)); // t(s)/(1/f) = ticks ns/1000/1000000
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PWMPulseWidthSet(PWM0_BASE, PWM_OUT_0 + (uint32_t)(configuration->channel - 1), configuration->pulse / 1000 * (sysPwmClock / 1000000));
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PWMGenEnable(PWM0_BASE, PWM_GEN_0);
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break;
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case '1':
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PWMGenPeriodSet(PWM0_BASE, PWM_GEN_1, configuration->period / 1000 * (sysPwmClock / 1000000));
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PWMPulseWidthSet(PWM0_BASE, PWM_OUT_0 + (uint32_t)(configuration->channel - 1), configuration->pulse / 1000 * (sysPwmClock / 1000000));
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PWMGenEnable(PWM0_BASE, PWM_GEN_1);
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break;
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case '2':
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PWMGenPeriodSet(PWM0_BASE, PWM_GEN_2, configuration->period / 1000 * (sysPwmClock / 1000000));
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PWMPulseWidthSet(PWM0_BASE, PWM_OUT_0 + (uint32_t)(configuration->channel - 1), configuration->pulse / 1000 * (sysPwmClock / 1000000));
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PWMGenEnable(PWM0_BASE, PWM_GEN_2);
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break;
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case '3':
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PWMGenPeriodSet(PWM0_BASE, PWM_GEN_3, configuration->period / 1000 * (sysPwmClock / 1000000));
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PWMPulseWidthSet(PWM0_BASE, PWM_OUT_0 + (uint32_t)(configuration->channel - 1), configuration->pulse / 1000 * (sysPwmClock / 1000000));
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PWMGenEnable(PWM0_BASE, PWM_GEN_3);
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break;
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case '4':
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PWMGenPeriodSet(PWM1_BASE, PWM_GEN_0, configuration->period / 1000 * (sysPwmClock / 1000000));
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PWMPulseWidthSet(PWM1_BASE, PWM_OUT_0 + (uint32_t)(configuration->channel - 1), configuration->pulse / 1000 * (sysPwmClock / 1000000));
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PWMGenEnable(PWM1_BASE, PWM_GEN_0);
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break;
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case '5':
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PWMGenPeriodSet(PWM1_BASE, PWM_GEN_1, configuration->period / 1000 * (sysPwmClock / 1000000));
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PWMPulseWidthSet(PWM1_BASE, PWM_OUT_2 + (uint32_t)(configuration->channel - 1), configuration->pulse / 1000 * (sysPwmClock / 1000000));
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PWMGenEnable(PWM1_BASE, PWM_GEN_1);
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break;
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case '6':
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PWMGenPeriodSet(PWM1_BASE, PWM_GEN_2, configuration->period / 1000 * (sysPwmClock / 1000000));
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PWMPulseWidthSet(PWM1_BASE, PWM_OUT_4 + (uint32_t)(configuration->channel - 1), configuration->pulse / 1000 * (sysPwmClock / 1000000));
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PWMGenEnable(PWM1_BASE, PWM_GEN_2);
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break;
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case '7':
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PWMGenPeriodSet(PWM1_BASE, PWM_GEN_3, configuration->period / 1000 * (sysPwmClock / 1000000));
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PWMPulseWidthSet(PWM1_BASE, PWM_OUT_6 + (uint32_t)(configuration->channel - 1), configuration->pulse / 1000 * (sysPwmClock / 1000000));
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PWMGenEnable(PWM1_BASE, PWM_GEN_3);
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break;
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default:
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break;
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}
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return RT_EOK;
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2020-06-24 19:54:42 +08:00
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}
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static rt_err_t tm4c123_pwm_control(struct rt_device_pwm *device, int cmd, void *arg)
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2020-07-01 23:44:57 +08:00
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2020-06-24 19:54:42 +08:00
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{
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struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg;
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2020-07-01 23:44:57 +08:00
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2020-06-24 19:54:42 +08:00
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switch (cmd)
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{
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case PWM_CMD_ENABLE:
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2020-07-01 23:44:57 +08:00
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return drv_pwm_enable(device->parent.parent.name, configuration, RT_TRUE);
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2020-06-24 19:54:42 +08:00
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case PWM_CMD_DISABLE:
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2020-07-01 23:44:57 +08:00
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return drv_pwm_enable(device->parent.parent.name, configuration, RT_FALSE);
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2020-06-24 19:54:42 +08:00
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case PWM_CMD_SET:
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2020-07-01 23:44:57 +08:00
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return drv_pwm_set(device->parent.parent.name, configuration);
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2020-06-24 19:54:42 +08:00
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case PWM_CMD_GET:
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2020-07-01 23:44:57 +08:00
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return drv_pwm_get(device->parent.parent.name, configuration);
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2020-06-24 19:54:42 +08:00
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default:
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return RT_EINVAL;
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}
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}
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static rt_err_t tm4c123_hw_pwm_init(struct tm4c123_pwm *device)
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{
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2020-07-01 23:44:57 +08:00
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rt_err_t result = RT_EOK;
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RT_ASSERT(device != RT_NULL);
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2020-06-24 19:54:42 +08:00
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2020-07-01 23:44:57 +08:00
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pwm_hw_config();
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switch (device->config->name[3])
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{
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case '0':
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PWMGenConfigure(PWM0_BASE, PWM_GEN_0, device->config->counterMode |
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device->config->syncMode);
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break;
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case '1':
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PWMGenConfigure(PWM0_BASE, PWM_GEN_1, device->config->counterMode |
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device->config->syncMode);
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break;
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case '2':
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PWMGenConfigure(PWM0_BASE, PWM_GEN_2, device->config->counterMode |
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device->config->syncMode);
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break;
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case '3':
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PWMGenConfigure(PWM0_BASE, PWM_GEN_3, device->config->counterMode |
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device->config->syncMode);
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break;
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case '4':
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PWMGenConfigure(PWM1_BASE, PWM_GEN_0, device->config->counterMode |
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device->config->syncMode);
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break;
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case '5':
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PWMGenConfigure(PWM1_BASE, PWM_GEN_1, device->config->counterMode |
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device->config->syncMode);
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break;
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case '6':
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PWMGenConfigure(PWM1_BASE, PWM_GEN_2, device->config->counterMode |
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device->config->syncMode);
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break;
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case '7':
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PWMGenConfigure(PWM1_BASE, PWM_GEN_3, device->config->counterMode |
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device->config->syncMode);
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break;
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default:
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LOG_E("%s PWMGenConfigure failed", device->config->name);
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result = -RT_ERROR;
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return result;
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}
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2020-06-24 19:54:42 +08:00
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2020-07-01 23:44:57 +08:00
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return result;
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}
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2020-06-24 19:54:42 +08:00
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int rt_hw_pwm_init(void)
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{
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2020-07-01 23:44:57 +08:00
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int i = 0;
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rt_size_t obj_num = sizeof(pwm_obj) / sizeof(struct tm4c123_pwm);
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rt_err_t result = RT_EOK;
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for (i = 0 ; i < obj_num; i++)
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{
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pwm_obj[i].config = &pwm_config[i];
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pwm_obj[i].pwm_device.ops = &drv_ops;
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/*pwm_init*/
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if (tm4c123_hw_pwm_init(&pwm_obj[i]) != RT_EOK)
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{
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LOG_E("%s init failed", pwm_obj[i].config->name);
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result = -RT_ERROR;
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return result;
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}
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else
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{
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LOG_D("%s init success", pwm_obj[i].config->name);
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/* register pwm device */
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if (rt_device_pwm_register(&pwm_obj[i].pwm_device, pwm_obj[i].config->name, &drv_ops, RT_NULL) == RT_EOK)
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{
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LOG_D("%s register success", pwm_obj[i].config->name);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
LOG_E("%s register failed", pwm_obj[i].config->name);
|
2020-06-24 19:54:42 +08:00
|
|
|
result = -RT_ERROR;
|
2020-07-01 23:44:57 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return result;
|
2020-06-24 19:54:42 +08:00
|
|
|
}
|
|
|
|
|
2020-07-01 23:44:57 +08:00
|
|
|
#endif /* RT_USING_PWM */
|
2020-06-24 19:54:42 +08:00
|
|
|
|
2021-03-21 22:23:24 +08:00
|
|
|
/************************** end of file ******************/
|