2017-08-22 15:52:57 +08:00
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/*
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2021-04-09 10:52:34 +08:00
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* Copyright (c) 2006-2021, RT-Thread Development Team
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2017-08-22 15:52:57 +08:00
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*
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2021-04-09 10:52:34 +08:00
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* SPDX-License-Identifier: Apache-2.0
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2017-08-22 15:52:57 +08:00
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*
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* Change Logs:
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* Date Author Notes
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* 2009-09-22 Bernard add board.h to this bsp
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*/
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// <<< Use Configuration Wizard in Context Menu >>>
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#ifndef __BOARD_H__
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#define __BOARD_H__
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#include <gd32f4xx.h>
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2017-08-23 19:19:52 +08:00
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#define EXT_SDRAM_BEGIN (0xC0000000U) /* the begining address of external SDRAM */
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#define EXT_SDRAM_END (EXT_SDRAM_BEGIN + (32U * 1024 * 1024)) /* the end address of external SDRAM */
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2017-08-22 15:52:57 +08:00
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// <o> Internal SRAM memory size[Kbytes] <8-64>
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2021-03-12 00:03:36 +08:00
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// <i>Default: 64
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2017-08-22 15:52:57 +08:00
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#ifdef __ICCARM__
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// Use *.icf ram symbal, to avoid hardcode.
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extern char __ICFEDIT_region_RAM_end__;
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#define GD32_SRAM_END &__ICFEDIT_region_RAM_end__
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#else
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#define GD32_SRAM_SIZE 128
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#define GD32_SRAM_END (0x20000000 + GD32_SRAM_SIZE * 1024)
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#endif
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#ifdef __CC_ARM
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extern int Image$$RW_IRAM1$$ZI$$Limit;
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#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit)
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#elif __ICCARM__
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#pragma section="HEAP"
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#define HEAP_BEGIN (__segment_end("HEAP"))
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#else
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extern int __bss_end;
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#define HEAP_BEGIN (&__bss_end)
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#endif
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#define HEAP_END GD32_SRAM_END
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#endif
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//*** <<< end of configuration section >>> ***
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