111 lines
3.5 KiB
Plaintext
111 lines
3.5 KiB
Plaintext
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#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m7 -E -x c
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/*
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** ###################################################################
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** Processors: MIMXRT1021CAF4A
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** MIMXRT1021CAG4A
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** MIMXRT1021DAF5A
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** MIMXRT1021DAG5A
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**
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** Compiler: Keil ARM C/C++ Compiler
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** Reference manual: IMXRT1020RM Rev.1, 12/2018 | IMXRT1020SRM Rev.3
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** Version: rev. 0.1, 2017-06-06
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** Build: b210709
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**
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** Abstract:
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** Linker file for the Keil ARM C/C++ Compiler
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**
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** Copyright 2016 Freescale Semiconductor, Inc.
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** Copyright 2016-2021 NXP
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** All rights reserved.
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**
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** SPDX-License-Identifier: BSD-3-Clause
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**
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** http: www.nxp.com
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** mail: support@nxp.com
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**
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** ###################################################################
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*/
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#define m_interrupts_start 0x80000000
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#define m_interrupts_size 0x00000400
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#define m_text_start 0x80000400
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#define m_text_size 0x001FFC00
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#define m_qacode_start 0x00000000
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#define m_qacode_size 0x00010000
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#define m_data_start 0x20200000
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#define m_data_size 0x00020000
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#define m_data2_start 0x20000000
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#define m_data2_size 0x00010000
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#define m_data3_start 0x80200000
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#define m_data3_size 0x01C00000
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#define m_ncache_start 0x81E00000
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#define m_ncache_size 0x00200000
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/* Sizes */
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#if (defined(__stack_size__))
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#define Stack_Size __stack_size__
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#else
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#define Stack_Size 0x0400
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#endif
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#if (defined(__heap_size__))
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#define Heap_Size __heap_size__
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#else
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#define Heap_Size 0x0400
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#endif
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LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
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VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
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* (.isr_vector,+FIRST)
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}
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ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
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* (InRoot$$Sections)
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.ANY (+RO)
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}
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VECTOR_RAM m_interrupts_start EMPTY 0 {
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}
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#if (defined(__heap_noncacheable__))
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RW_m_data m_data_start m_data_size-Stack_Size { ; RW data
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#else
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RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
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#endif
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.ANY (+RW +ZI)
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* (*m_usb_dma_init_data)
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* (*m_usb_dma_noninit_data)
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}
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#if (!defined(__heap_noncacheable__))
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ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
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}
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#endif
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ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
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}
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RW_m_ram_text m_qacode_start m_qacode_size { ;
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* (CodeQuickAccess)
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}
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RW_m_data2 m_data2_start m_data2_size { ;
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* (DataQuickAccess)
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}
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#if (defined(__heap_noncacheable__))
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RW_m_ncache m_ncache_start m_ncache_size - Heap_Size { ; ncache RW data
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#else
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RW_m_ncache m_ncache_start m_ncache_size { ; ncache RW data
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#endif
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* (NonCacheable.init)
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* (*NonCacheable)
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}
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#if (defined(__heap_noncacheable__))
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ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
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}
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RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache)-Heap_Size { ; Empty region added for MPU configuration
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#else
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RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration
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#endif
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}
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}
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