216 lines
9.8 KiB
C
216 lines
9.8 KiB
C
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//*****************************************************************************
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//
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// am_reg_jedec.h
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//! @file
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//!
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//! @brief Register macros for the JEDEC module
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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// Copyright (c) 2017, Ambiq Micro
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from this
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// software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
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//
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//*****************************************************************************
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#ifndef AM_REG_JEDEC_H
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#define AM_REG_JEDEC_H
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//*****************************************************************************
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//
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// Instance finder. (1 instance(s) available)
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//
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//*****************************************************************************
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#define AM_REG_JEDEC_NUM_MODULES 1
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#define AM_REG_JEDECn(n) \
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(REG_JEDEC_BASEADDR + 0x00000000 * n)
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//*****************************************************************************
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//
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// Register offsets.
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//
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//*****************************************************************************
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#define AM_REG_JEDEC_PID4_O 0xF0000FD0
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#define AM_REG_JEDEC_PID5_O 0xF0000FD4
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#define AM_REG_JEDEC_PID6_O 0xF0000FD8
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#define AM_REG_JEDEC_PID7_O 0xF0000FDC
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#define AM_REG_JEDEC_PID0_O 0xF0000FE0
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#define AM_REG_JEDEC_PID1_O 0xF0000FE4
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#define AM_REG_JEDEC_PID2_O 0xF0000FE8
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#define AM_REG_JEDEC_PID3_O 0xF0000FEC
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#define AM_REG_JEDEC_CID0_O 0xF0000FF0
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#define AM_REG_JEDEC_CID1_O 0xF0000FF4
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#define AM_REG_JEDEC_CID2_O 0xF0000FF8
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#define AM_REG_JEDEC_CID3_O 0xF0000FFC
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//*****************************************************************************
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//
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// JEDEC_PID4 - JEP Continuation Register
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//
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//*****************************************************************************
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// Contains the JEP Continuation bits.
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#define AM_REG_JEDEC_PID4_JEPCONT_S 0
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#define AM_REG_JEDEC_PID4_JEPCONT_M 0x0000000F
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#define AM_REG_JEDEC_PID4_JEPCONT(n) (((uint32_t)(n) << 0) & 0x0000000F)
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//*****************************************************************************
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//
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// JEDEC_PID5 - JEP reserved Register
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//
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//*****************************************************************************
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// Contains the value of 0x00000000.
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#define AM_REG_JEDEC_PID5_VALUE_S 0
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#define AM_REG_JEDEC_PID5_VALUE_M 0xFFFFFFFF
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#define AM_REG_JEDEC_PID5_VALUE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
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//*****************************************************************************
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//
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// JEDEC_PID6 - JEP reserved Register
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//
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//*****************************************************************************
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// Contains the value of 0x00000000.
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#define AM_REG_JEDEC_PID6_VALUE_S 0
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#define AM_REG_JEDEC_PID6_VALUE_M 0xFFFFFFFF
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#define AM_REG_JEDEC_PID6_VALUE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
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//*****************************************************************************
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//
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// JEDEC_PID7 - JEP reserved Register
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//
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//*****************************************************************************
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// Contains the value of 0x00000000.
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#define AM_REG_JEDEC_PID7_VALUE_S 0
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#define AM_REG_JEDEC_PID7_VALUE_M 0xFFFFFFFF
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#define AM_REG_JEDEC_PID7_VALUE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
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//*****************************************************************************
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//
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// JEDEC_PID0 - Ambiq Partnum low byte
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//
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//*****************************************************************************
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// Contains the low 8 bits of the Ambiq Micro device part number.
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#define AM_REG_JEDEC_PID0_PNL8_S 0
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#define AM_REG_JEDEC_PID0_PNL8_M 0x000000FF
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#define AM_REG_JEDEC_PID0_PNL8(n) (((uint32_t)(n) << 0) & 0x000000FF)
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//*****************************************************************************
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//
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// JEDEC_PID1 - Ambiq part number high-nibble, JEPID low-nibble.
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//
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//*****************************************************************************
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// Contains the low 4 bits of the Ambiq Micro JEDEC JEP-106 ID. The full JEPID
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// is therefore 0x9B.
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#define AM_REG_JEDEC_PID1_JEPIDL_S 4
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#define AM_REG_JEDEC_PID1_JEPIDL_M 0x000000F0
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#define AM_REG_JEDEC_PID1_JEPIDL(n) (((uint32_t)(n) << 4) & 0x000000F0)
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// Contains the high 4 bits of the Ambiq Micro device part number.
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#define AM_REG_JEDEC_PID1_PNH4_S 0
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#define AM_REG_JEDEC_PID1_PNH4_M 0x0000000F
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#define AM_REG_JEDEC_PID1_PNH4(n) (((uint32_t)(n) << 0) & 0x0000000F)
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//*****************************************************************************
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//
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// JEDEC_PID2 - Ambiq chip revision low-nibble, JEPID high-nibble
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//
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//*****************************************************************************
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// Contains the high 4 bits of the Ambiq Micro CHIPREV (see also
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// MCUCTRL.CHIPREV). Note that this field will change with each revision of the
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// chip.
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#define AM_REG_JEDEC_PID2_CHIPREVH4_S 4
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#define AM_REG_JEDEC_PID2_CHIPREVH4_M 0x000000F0
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#define AM_REG_JEDEC_PID2_CHIPREVH4(n) (((uint32_t)(n) << 4) & 0x000000F0)
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// Contains the high 3 bits of the Ambiq Micro JEPID. Note that bit3 of this
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// field is hard-coded to 1. The full JEPID is therefore 0x9B.
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#define AM_REG_JEDEC_PID2_JEPIDH_S 0
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#define AM_REG_JEDEC_PID2_JEPIDH_M 0x0000000F
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#define AM_REG_JEDEC_PID2_JEPIDH(n) (((uint32_t)(n) << 0) & 0x0000000F)
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//*****************************************************************************
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//
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// JEDEC_PID3 - Ambiq chip revision high-nibble.
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//
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//*****************************************************************************
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// Contains the low 4 bits of the Ambiq Micro CHIPREV (see also
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// MCUCTRL.CHIPREV). Note that this field will change with each revision of the
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// chip.
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#define AM_REG_JEDEC_PID3_CHIPREVL4_S 4
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#define AM_REG_JEDEC_PID3_CHIPREVL4_M 0x000000F0
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#define AM_REG_JEDEC_PID3_CHIPREVL4(n) (((uint32_t)(n) << 4) & 0x000000F0)
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// This field is hard-coded to 0x0.
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#define AM_REG_JEDEC_PID3_ZERO_S 0
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#define AM_REG_JEDEC_PID3_ZERO_M 0x0000000F
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#define AM_REG_JEDEC_PID3_ZERO(n) (((uint32_t)(n) << 0) & 0x0000000F)
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//*****************************************************************************
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//
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// JEDEC_CID0 - Coresight ROM Table.
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//
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//*****************************************************************************
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// Coresight ROM Table, CID0.
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#define AM_REG_JEDEC_CID0_CID_S 0
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#define AM_REG_JEDEC_CID0_CID_M 0x000000FF
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#define AM_REG_JEDEC_CID0_CID(n) (((uint32_t)(n) << 0) & 0x000000FF)
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//*****************************************************************************
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//
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// JEDEC_CID1 - Coresight ROM Table.
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//
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//*****************************************************************************
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// Coresight ROM Table, CID1.
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#define AM_REG_JEDEC_CID1_CID_S 0
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#define AM_REG_JEDEC_CID1_CID_M 0x000000FF
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#define AM_REG_JEDEC_CID1_CID(n) (((uint32_t)(n) << 0) & 0x000000FF)
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//*****************************************************************************
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//
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// JEDEC_CID2 - Coresight ROM Table.
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//
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//*****************************************************************************
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// Coresight ROM Table, CID2.
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#define AM_REG_JEDEC_CID2_CID_S 0
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#define AM_REG_JEDEC_CID2_CID_M 0x000000FF
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#define AM_REG_JEDEC_CID2_CID(n) (((uint32_t)(n) << 0) & 0x000000FF)
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//*****************************************************************************
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//
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// JEDEC_CID3 - Coresight ROM Table.
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//
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//*****************************************************************************
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// Coresight ROM Table, CID3.
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#define AM_REG_JEDEC_CID3_CID_S 0
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#define AM_REG_JEDEC_CID3_CID_M 0x000000FF
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#define AM_REG_JEDEC_CID3_CID(n) (((uint32_t)(n) << 0) & 0x000000FF)
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#endif // AM_REG_JEDEC_H
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