2023-03-29 18:31:05 +08:00
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/*
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* Copyright (c) 2006-2020, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-04-16 bigmagic first version
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* 2021-12-28 GuEe-GUI add smp support
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* 2023-03-28 WangXiaoyao sync works & memory layout fixups
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* code formats
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*/
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2024-04-11 00:02:49 +08:00
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#define DBG_TAG "board"
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#define DBG_LVL DBG_INFO
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#include <rtdbg.h>
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2023-03-29 18:31:05 +08:00
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#include <rthw.h>
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#include <rtthread.h>
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#include <mm_aspace.h>
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#include "board.h"
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#include "drv_uart.h"
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#include "cp15.h"
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#include "mmu.h"
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#include "mbox.h"
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#include <mm_page.h>
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#ifdef RT_USING_SMART
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#include <lwp_arch.h>
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#endif
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extern size_t MMUTable[];
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size_t gpio_base_addr = GPIO_BASE_ADDR;
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size_t uart_base_addr = UART_BASE;
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size_t gic_base_addr = GIC_V2_BASE;
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size_t arm_timer_base = ARM_TIMER_BASE;
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size_t pactl_cs_base = PACTL_CS_ADDR;
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size_t stimer_base_addr = STIMER_BASE;
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size_t mmc2_base_addr = MMC2_BASE_ADDR;
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size_t videocore_mbox = VIDEOCORE_MBOX;
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size_t mbox_addr = MBOX_ADDR;
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size_t wdt_base_addr = WDT_BASE;
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uint8_t *mac_reg_base_addr = (uint8_t *)MAC_REG;
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uint8_t *eth_send_no_cache = (uint8_t *)SEND_DATA_NO_CACHE;
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uint8_t *eth_recv_no_cache = (uint8_t *)RECV_DATA_NO_CACHE;
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#ifdef RT_USING_SMART
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struct mem_desc platform_mem_desc[] = {
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{KERNEL_VADDR_START, KERNEL_VADDR_START + 0x0fffffff, (rt_size_t)ARCH_MAP_FAILED, NORMAL_MEM}
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};
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#else
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struct mem_desc platform_mem_desc[] = {
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2024-04-11 00:02:49 +08:00
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{0x00200000, (256ul << 20) - 1, 0x00200000, NORMAL_MEM},
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2023-03-29 18:31:05 +08:00
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{0xFC000000, 0x000100000000 - 1, 0xFC000000, DEVICE_MEM},
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};
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#endif
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const rt_uint32_t platform_mem_desc_size = sizeof(platform_mem_desc)/sizeof(platform_mem_desc[0]);
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void idle_wfi(void)
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{
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asm volatile ("wfi");
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}
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/**
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* This function will initialize board
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*/
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extern size_t MMUTable[];
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int rt_hw_gtimer_init(void);
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rt_region_t init_page_region = {
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PAGE_START,
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PAGE_END,
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};
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/**
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* Initialize the Hardware related stuffs. Called from rtthread_startup()
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* after interrupt disabled.
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*/
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void rt_hw_board_init(void)
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{
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rt_hw_earlycon_ioremap_early();
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2023-03-29 18:31:05 +08:00
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/* io device remap */
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#ifdef RT_USING_SMART
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rt_hw_mmu_map_init(&rt_kernel_space, (void*)0xfffffffff0000000, 0x10000000, MMUTable, PV_OFFSET);
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#else
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2024-04-11 00:02:49 +08:00
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rt_hw_mmu_map_init(&rt_kernel_space, (void*)0x080000000000, 0x10000000, MMUTable, 0);
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#endif /* RT_USING_SMART */
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2023-03-29 18:31:05 +08:00
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rt_page_init(init_page_region);
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rt_hw_mmu_setup(&rt_kernel_space, platform_mem_desc, platform_mem_desc_size);
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/* map peripheral address to virtual address */
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#ifdef RT_USING_HEAP
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/* initialize system heap */
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rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
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#endif
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/* initialize hardware interrupt */
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rt_hw_interrupt_init();
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//gpio
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gpio_base_addr = (size_t)rt_ioremap((void*)GPIO_BASE_ADDR, 0x1000);
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//pactl
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pactl_cs_base = (size_t)rt_ioremap((void*)PACTL_CS_ADDR, 0x1000);
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//stimer
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stimer_base_addr = (size_t)rt_ioremap((void*)STIMER_BASE, 0x1000);
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//mmc2_base_addr
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mmc2_base_addr = (size_t)rt_ioremap((void*)MMC2_BASE_ADDR, 0x1000);
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//mbox
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videocore_mbox = (size_t)rt_ioremap((void*)VIDEOCORE_MBOX, 0x1000);
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// mbox msg
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mbox = (volatile unsigned int *)rt_pages_alloc(0);
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//wdt
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wdt_base_addr = (size_t)rt_ioremap((void*)WDT_BASE, 0x1000);
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//mac
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mac_reg_base_addr = (void *)rt_ioremap((void*)MAC_REG, 0x80000);
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// eth data
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eth_send_no_cache = (void *)rt_pages_alloc(rt_page_bits(0x200000));
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eth_recv_no_cache = (void *)rt_pages_alloc(rt_page_bits(0x200000));
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/* initialize uart */
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rt_hw_uart_init();
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/* initialize timer for os tick */
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rt_hw_gtimer_init();
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#ifdef RT_USING_CONSOLE
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/* set console device */
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rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
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#endif /* RT_USING_CONSOLE */
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#ifdef RT_USING_COMPONENTS_INIT
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rt_components_board_init();
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#endif
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rt_thread_idle_sethook(idle_wfi);
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}
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#ifdef RT_USING_SMP
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#include <gic.h>
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void rt_hw_mmu_ktbl_set(unsigned long tbl);
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void _secondary_cpu_entry(void);
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static unsigned long cpu_release_paddr[] =
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{
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[0] = 0xd8,
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[1] = 0xe0,
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[2] = 0xe8,
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[3] = 0xf0,
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[4] = 0x00
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};
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void rt_hw_secondary_cpu_up(void)
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{
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int i;
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void *release_addr;
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for (i = 1; i < RT_CPUS_NR && cpu_release_paddr[i]; ++i)
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{
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release_addr = rt_ioremap((void *)cpu_release_paddr[i], sizeof(cpu_release_paddr[0]));
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__asm__ volatile ("str %0, [%1]"::"rZ"((unsigned long)_secondary_cpu_entry + PV_OFFSET), "r"(release_addr));
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rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, release_addr, sizeof(release_addr));
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asm volatile ("dsb sy");
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asm volatile ("sev");
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}
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}
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void rt_hw_secondary_cpu_bsp_start(void)
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{
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rt_hw_spin_lock(&_cpus_lock);
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rt_hw_mmu_ktbl_set((unsigned long)MMUTable);
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rt_hw_vector_init();
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arm_gic_cpu_init(0, 0);
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rt_hw_gtimer_init();
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rt_kprintf("\rcpu %d boot success\n", rt_hw_cpu_id());
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rt_system_scheduler_start();
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}
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void rt_hw_secondary_cpu_idle_exec(void)
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{
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asm volatile ("wfe":::"memory", "cc");
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}
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#endif
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