2020-01-15 16:46:19 +08:00
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/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-01-15 bigmagic the first version
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*/
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2020-01-10 10:38:21 +08:00
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#ifndef MMU_H__
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#define MMU_H__
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#include <rtthread.h>
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#include <rthw.h>
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#include <board.h>
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#include "cp15.h"
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#define DESC_SEC (0x2)
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#define CB (3<<2) //cache_on, write_back
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#define CNB (2<<2) //cache_on, write_through
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#define NCB (1<<2) //cache_off,WR_BUF on
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#define NCNB (0<<2) //cache_off,WR_BUF off
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#define AP_RW (3<<10) //supervisor=RW, user=RW
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#define AP_RO (2<<10) //supervisor=RW, user=RO
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#define XN (1<<4) // eXecute Never
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#define SHARED (1<<16) /* shareable */
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#define SHAREDEVICE (1<<2) /* shared device */
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#define STRONGORDER (0<<2) /* strong ordered */
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#define MEMWBWA ((1<<12)|(3<<2)) /* write back, write allocate */
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#define DOMAIN_FAULT (0x0)
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#define DOMAIN_CHK (0x1)
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#define DOMAIN_NOTCHK (0x3)
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#define DOMAIN0 (0x0<<5)
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#define DOMAIN1 (0x1<<5)
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#define DOMAIN0_ATTR (DOMAIN_CHK<<0)
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#define DOMAIN1_ATTR (DOMAIN_FAULT<<2)
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/* Read/Write, cache, write back */
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#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC)
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/* Read/Write, cache, write through */
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#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC)
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/* Read/Write without cache and write buffer */
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#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC)
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/* Read/Write without cache and write buffer, no execute */
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#define RW_NCNBXN (AP_RW|DOMAIN0|NCNB|DESC_SEC|XN)
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/* Read/Write without cache and write buffer */
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#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC)
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/* device mapping type */
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#define DEVICE_MEM (SHARED|SHAREDEVICE|RW_NCNBXN)
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/* normal memory mapping type */
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#define NORMAL_MEM (SHARED|AP_RW|DOMAIN0|MEMWBWA|DESC_SEC)
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#define STRONG_ORDER_MEM (SHARED|AP_RO|XN|DESC_SEC)
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#define BUS_ADDRESS(phys) (((phys) & ~0xC0000000) | 0xC0000000)
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void rt_hw_change_mmu_table(rt_uint32_t vaddrStart,
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rt_uint32_t size,
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rt_uint32_t paddrStart, rt_uint32_t attr);
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#endif
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