299 lines
7.4 KiB
C
299 lines
7.4 KiB
C
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/*
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* Copyright (c) 2006-2019, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2019-07-29 zdzn first version
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include "board.h"
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#include "drv_uart.h"
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#include "drv_timer.h"
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#include "cp15.h"
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#ifdef RT_USING_SMP
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extern void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler);
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void ipi_handler(){
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rt_scheduler_ipi_handler(0,RT_NULL);
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}
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#endif
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void rt_hw_timer_isr(int vector, void *parameter)
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{
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ARM_TIMER_IRQCLR = 0;
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rt_tick_increase();
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}
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int rt_hw_timer_init()
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{
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__DSB();
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rt_hw_interrupt_install(IRQ_ARM_TIMER, rt_hw_timer_isr, RT_NULL, "tick");
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rt_hw_interrupt_umask(IRQ_ARM_TIMER);
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/* timer_clock = apb_clock/(pre_divider + 1) */
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ARM_TIMER_PREDIV = (250 - 1);
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ARM_TIMER_RELOAD = 0;
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ARM_TIMER_LOAD = 0;
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ARM_TIMER_IRQCLR = 0;
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ARM_TIMER_CTRL = 0;
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ARM_TIMER_RELOAD = 10000;
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ARM_TIMER_LOAD = 10000;
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/* 23-bit counter, enable interrupt, enable timer */
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ARM_TIMER_CTRL = (1 << 1) | (1 << 5) | (1 << 7);
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return 0;
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}
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void idle_wfi(void)
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{
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asm volatile ("wfi");
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}
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#define MMU_LEVEL_MASK 0x1ffUL
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#define MMU_MAP_ERROR_VANOTALIGN -1
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#define MMU_MAP_ERROR_PANOTALIGN -2
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#define MMU_MAP_ERROR_NOPAGE -3
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#define MMU_MAP_ERROR_CONFLICT -4
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unsigned char main_tbl[4096] __attribute__((aligned (4096)));
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unsigned char __page_start[4096*100] __attribute__((aligned (4096)));
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unsigned long __page_off = 0;
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unsigned long get_free_page(void) {
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__page_off += 4096;
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return (unsigned long)(__page_start + __page_off - 4096);
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}
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#define MEM_ATTR_MEM ((0x1UL << 10) | (0x2UL << 8) | (0x0UL << 6) | (0x1UL << 2))
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#define MEM_ATTR_IO ((0x1UL << 10) | (0x2UL << 8) | (0x0UL << 6) | (0x2UL << 2))
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static int map_single_page_2M(unsigned long* lv0_tbl, unsigned long va, unsigned long pa, unsigned long attr) {
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int level;
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unsigned long* cur_lv_tbl = lv0_tbl;
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unsigned long page;
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unsigned long off;
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int level_shift = 39;
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if (va & (0x200000UL - 1)) {
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return MMU_MAP_ERROR_VANOTALIGN;
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}
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if (pa & (0x200000UL - 1)) {
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return MMU_MAP_ERROR_PANOTALIGN;
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}
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for (level = 0; level < 2; level++) {
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off = (va >> level_shift);
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off &= MMU_LEVEL_MASK;
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if ((cur_lv_tbl[off] & 1) == 0) {
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page = get_free_page();
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if (!page) {
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return MMU_MAP_ERROR_NOPAGE;
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}
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rt_memset((void *)page, 0, 4096);
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cur_lv_tbl[off] = page | 0x3UL;
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}
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page = cur_lv_tbl[off];
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if (!(page & 0x2)) {
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//is block! error!
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return MMU_MAP_ERROR_CONFLICT;
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}
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cur_lv_tbl = (unsigned long*)(page & 0x0000fffffffff000UL);
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level_shift -= 9;
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}
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attr &= 0xfff0000000000ffcUL;
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pa |= (attr | 0x1UL); //block
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off = (va >> 21);
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off &= MMU_LEVEL_MASK;
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cur_lv_tbl[off] = pa;
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return 0;
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}
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int armv8_map_2M(unsigned long* lv0_tbl, unsigned long va, unsigned long pa, int count, unsigned long attr)
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{
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int i;
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int ret;
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if (va & (0x200000 - 1))
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{
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return -1;
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}
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if (pa & (0x200000 - 1))
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{
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return -1;
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}
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for (i = 0; i < count; i++)
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{
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ret = map_single_page_2M(lv0_tbl, va, pa, attr);
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va += 0x200000;
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pa += 0x200000;
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if (ret != 0)
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{
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return ret;
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}
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}
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return 0;
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}
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/**
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* Initialize the Hardware related stuffs. Called from rtthread_startup()
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* after interrupt disabled.
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*/
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void rt_hw_board_init(void)
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{
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/* mmu set */
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unsigned long val64;
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unsigned long val32; //val32不是uint32_t,val32只是表示相关的那个寄存器是32位的
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int ret;
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val64 = 0x007f6eUL;
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asm volatile("msr MAIR_EL1, %0\n dsb sy\n"::"r"(val64));
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asm volatile("mrs %0, MAIR_EL1\n dsb sy\n":"=r"(val64));
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//TCR_EL1
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val32 = (16UL << 0)
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| (0x0UL << 6)
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| (0x0UL << 7)
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| (0x3UL << 8)
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| (0x3UL << 10)
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| (0x2UL << 12)
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| (0x0UL << 14)
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| (0x0UL << 16)
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| (0x0UL << 22)
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| (0x1UL << 23)
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| (0x2UL << 30)
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| (0x1UL << 32)
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| (0x0UL << 35)
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| (0x0UL << 36)
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| (0x0UL << 37)
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| (0x0UL << 38);
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asm volatile("msr TCR_EL1, %0\n"::"r"(val32));
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asm volatile("mrs %0, TCR_EL1\n":"=r"(val32));
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asm volatile("msr TTBR0_EL1, %0\n dsb sy\n"::"r"(main_tbl));
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asm volatile("mrs %0, TTBR0_EL1\n dsb sy\n":"=r"(val64));
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rt_memset(main_tbl, 0, 4096);
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ret = armv8_map_2M((unsigned long *)main_tbl, 0x0, 0x0, 32, MEM_ATTR_MEM); //32*2M = 64M
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if (ret)
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{
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goto skip_mmu;
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}
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ret = armv8_map_2M((unsigned long *)main_tbl, 0x3f000000, 0x3f000000, 8, MEM_ATTR_IO); //8*2M = 16M
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if (ret)
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{
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goto skip_mmu;
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}
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//关闭指令cache
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__asm__ volatile("mrs %0, SCTLR_EL1\n":"=r"(val64));
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val64 &= ~0x1000; //disable I
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__asm__ volatile("dmb sy\n msr SCTLR_EL1, %0\n isb sy\n"::"r"(val64));
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//清除指令cache
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__asm__ volatile("IC IALLUIS\n dsb sy\n isb sy\n");
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//清除tlb
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__asm__ volatile("tlbi vmalle1\n dsb sy\n isb sy\n");
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//SCTLR_EL1, turn on mmu
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asm volatile("mrs %0, SCTLR_EL1\n":"=r"(val32));
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val32 |= 0x1005; //enable mmu, I C M
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asm volatile("dmb sy\n msr SCTLR_EL1, %0\nisb sy\n"::"r"(val32));
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skip_mmu:
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/* initialize hardware interrupt */
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rt_hw_interrupt_init(); // in libcpu/interrupt.c. Set some data structures, no operation on device
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rt_hw_vector_init(); // in libcpu/interrupt.c. == rt_cpu_vector_set_base((rt_ubase_t)&system_vectors);
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/* initialize uart */
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rt_hw_uart_init(); // driver/drv_uart.c
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/* initialize timer for os tick */
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rt_hw_timer_init();
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rt_thread_idle_sethook(idle_wfi);
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#ifdef RT_USING_CONSOLE
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/* set console device */
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rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
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#endif /* RT_USING_CONSOLE */
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#ifdef RT_USING_HEAP
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/* initialize memory system */
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rt_kprintf("heap: 0x%08x - 0x%08x\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
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rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
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#endif
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#ifdef RT_USING_COMPONENTS_INIT
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rt_components_board_init();
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#endif
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rt_kprintf("__page_off = %x\n", __page_off);
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}
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#ifdef RT_USING_SMP
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void _reset(void);
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void secondary_cpu_start(void);
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void rt_hw_secondary_cpu_up(void)
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{
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int i;
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int retry,val;
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rt_cpu_dcache_clean_flush();
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rt_cpu_icache_flush();
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/*TODO maybe, there is some bug */
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for(i=RT_CPUS_NR-1; i>0; i-- )
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{
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rt_kprintf("boot cpu:%d\n", i);
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setup_bootstrap_addr(i, (int)_reset);
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__SEV();
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__DSB();
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__ISB();
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retry = 10;
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rt_thread_delay(RT_TICK_PER_SECOND/1000);
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do
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{
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val = CORE_MAILBOX3_CLEAR(i);
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if (val == 0)
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{
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rt_kprintf("start OK: CPU %d \n",i);
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break;
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}
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rt_thread_delay(RT_TICK_PER_SECOND);
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retry --;
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if (retry <= 0)
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{
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rt_kprintf("can't start for CPU %d \n",i);
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break;
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}
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}while (1);
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}
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__DSB();
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__SEV();
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}
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void secondary_cpu_c_start(void)
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{
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uint32_t id;
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id = rt_hw_cpu_id();
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rt_kprintf("cpu = 0x%08x\n",id);
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rt_hw_timer_init();
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rt_kprintf("cpu %d startup.\n",id);
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rt_hw_vector_init();
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enable_cpu_ipi_intr(id);
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rt_hw_spin_lock(&_cpus_lock);
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rt_system_scheduler_start();
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}
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void rt_hw_secondary_cpu_idle_exec(void)
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{
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__WFE();
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}
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#endif
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