126 lines
6.6 KiB
C
126 lines
6.6 KiB
C
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////////////////////////////////////////////////////////////////////////////////
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/// @file reg_iwdg.h
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/// @author AE TEAM
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/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
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/// MM32 FIRMWARE LIBRARY.
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////////////////////////////////////////////////////////////////////////////////
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/// @attention
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///
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/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
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/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
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/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
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/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
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/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
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/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
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///
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/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
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////////////////////////////////////////////////////////////////////////////////
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// Define to prevent recursive inclusion
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#ifndef __REG_IWDG_H
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#define __REG_IWDG_H
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// Files includes
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#include <stdint.h>
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#include <stdbool.h>
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#include "types.h"
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#if defined ( __CC_ARM )
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#pragma anon_unions
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#endif
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////////////////////////////////////////////////////////////////////////////////
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/// @brief IWDG Base Address Definition
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////////////////////////////////////////////////////////////////////////////////
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#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) ///< Base Address: 0x40003000
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////////////////////////////////////////////////////////////////////////////////
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/// @brief IWDG Register Structure Definition
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////////////////////////////////////////////////////////////////////////////////
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typedef struct {
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__IO u32 KR; ///< Key Register offset: 0x00
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__IO u32 PR; ///< Prescaler Register offset: 0x04
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__IO u32 RLR; ///< Reload Register offset: 0x08
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__IO u32 SR; ///< Status Register offset: 0x0C
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__IO u32 CR; ///< Control Register offset: 0x10
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__IO u32 IGEN; ///< Interrupt Generator Register offset: 0x14
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__IO u32 CNT; ///< Interrupt Generator count Register offset: 0x18
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__IO u32 PS; ///< Prescaler count Register offset: 0x1C
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} IWDG_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief IWDG type pointer Definition
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////////////////////////////////////////////////////////////////////////////////
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#define IWDG ((IWDG_TypeDef*) IWDG_BASE)
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////////////////////////////////////////////////////////////////////////////////
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/// @brief IWDG_KR Register Bit Definition
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////////////////////////////////////////////////////////////////////////////////
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#define IWDG_KEYR_KEY_Pos (0)
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#define IWDG_KEYR_KEY (0xFFFFU << IWDG_KEYR_KEY_Pos) ///< Key Value
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////////////////////////////////////////////////////////////////////////////////
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/// @brief IWDG_PR Register Bit Definition
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////////////////////////////////////////////////////////////////////////////////
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#define IWDG_PR_PRE_Pos (0)
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#define IWDG_PR_PRE (0x07U << IWDG_PR_PRE_Pos) ///< Prescaler divided by 4
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#define IWDG_PR_PRE_DIV4 (0x00U << IWDG_PR_PRE_Pos) ///< Prescaler divided by 4
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#define IWDG_PR_PRE_DIV8 (0x01U << IWDG_PR_PRE_Pos) ///< Prescaler divided by 8
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#define IWDG_PR_PRE_DIV16 (0x02U << IWDG_PR_PRE_Pos) ///< Prescaler divided by 16
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#define IWDG_PR_PRE_DIV32 (0x03U << IWDG_PR_PRE_Pos) ///< Prescaler divided by 32
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#define IWDG_PR_PRE_DIV64 (0x04U << IWDG_PR_PRE_Pos) ///< Prescaler divided by 64
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#define IWDG_PR_PRE_DIV128 (0x05U << IWDG_PR_PRE_Pos) ///< Prescaler divided by 128
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#define IWDG_PR_PRE_DIV256 (0x06U << IWDG_PR_PRE_Pos) ///< Prescaler divided by 256
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////////////////////////////////////////////////////////////////////////////////
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/// @brief IWDG_RLR Register Bit Definition
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////////////////////////////////////////////////////////////////////////////////
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#define IWDG_RLR_RL_Pos (0)
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#define IWDG_RLR_RL (0x0FFFU << IWDG_RLR_RL_Pos) ///< Watchdog counter reload value
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////////////////////////////////////////////////////////////////////////////////
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/// @brief IWDG_SR Register Bit Definition
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////////////////////////////////////////////////////////////////////////////////
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#define IWDG_SR_PVU_Pos (0)
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#define IWDG_SR_PVU (0x01U << IWDG_SR_PVU_Pos) ///< Watchdog prescaler value update
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#define IWDG_SR_RVU_Pos (1)
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#define IWDG_SR_RVU (0x01U << IWDG_SR_RVU_Pos) ///< Watchdog counter reload value update
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#define IWDG_SR_IVU_Pos (2)
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#define IWDG_SR_IVU (0x01U << IWDG_SR_IVU_Pos)
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#define IWDG_SR_UPDATE_Pos (3)
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#define IWDG_SR_UPDATE (0x01U << IWDG_SR_UPDATE_Pos)
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////////////////////////////////////////////////////////////////////////////////
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/// @brief IWDG_CR Register Bit Definition
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////////////////////////////////////////////////////////////////////////////////
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#define IWDG_CR_IRQSEL_Pos (0)
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#define IWDG_CR_IRQSEL (0x01U << IWDG_CR_IRQSEL_Pos) ///< IWDG overflow operation selection
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#define IWDG_CR_IRQCLR_Pos (1)
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#define IWDG_CR_IRQCLR (0x01U << IWDG_CR_IRQCLR_Pos) ///< IWDG interrupt clear
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////////////////////////////////////////////////////////////////////////////////
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/// @brief IWDG_IGRN Register Bit Definition
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////////////////////////////////////////////////////////////////////////////////
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#define IWDG_IGEN_IGEN_Pos (0)
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#define IWDG_IGEN_IGEN (0xFFFU << IWDG_CR_IRQSEL_Pos) ///< IWDG Interrupt Generate value
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/// @}
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/// @}
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/// @}
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////////////////////////////////////////////////////////////////////////////////
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#endif
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////////////////////////////////////////////////////////////////////////////////
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