131 lines
5.0 KiB
C
131 lines
5.0 KiB
C
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/*
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* Copyright 2016-2020 NXP
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* All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _RTE_DEVICE_H
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#define _RTE_DEVICE_H
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#include "pin_mux.h"
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/* UART Select, UART0 - UART5. */
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/* User needs to provide the implementation of LPUARTX_GetFreq/LPUARTX_InitPins/LPUARTX_DeinitPins for the enabled
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* LPUART instance. */
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#define RTE_USART1 1
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#define RTE_USART1_DMA_EN 1
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#define RTE_USART2 0
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#define RTE_USART2_DMA_EN 0
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#define RTE_USART3 0
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#define RTE_USART3_DMA_EN 0
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#define RTE_USART4 0
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#define RTE_USART4_DMA_EN 0
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#define RTE_USART5 0
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#define RTE_USART5_DMA_EN 0
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#define RTE_USART6 0
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#define RTE_USART6_DMA_EN 0
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#define RTE_USART7 0
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#define RTE_USART7_DMA_EN 0
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#define RTE_USART8 0
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#define RTE_USART8_DMA_EN 0
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/* UART configuration. */
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#define RTE_USART1_PIN_INIT LPUART1_InitPins
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#define RTE_USART1_PIN_DEINIT LPUART1_DeinitPins
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#define RTE_USART1_DMA_TX_CH 0
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#define RTE_USART1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART1Tx
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#define RTE_USART1_DMA_TX_DMAMUX_BASE DMAMUX
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#define RTE_USART1_DMA_TX_DMA_BASE DMA0
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#define RTE_USART1_DMA_RX_CH 1
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#define RTE_USART1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART1Rx
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#define RTE_USART1_DMA_RX_DMAMUX_BASE DMAMUX
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#define RTE_USART1_DMA_RX_DMA_BASE DMA0
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#define RTE_USART2_PIN_INIT LPUART2_InitPins
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#define RTE_USART2_PIN_DEINIT LPUART2_DeinitPins
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#define RTE_USART2_DMA_TX_CH 2
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#define RTE_USART2_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART2Tx
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#define RTE_USART2_DMA_TX_DMAMUX_BASE DMAMUX
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#define RTE_USART2_DMA_TX_DMA_BASE DMA0
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#define RTE_USART2_DMA_RX_CH 3
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#define RTE_USART2_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART2Rx
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#define RTE_USART2_DMA_RX_DMAMUX_BASE DMAMUX
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#define RTE_USART2_DMA_RX_DMA_BASE DMA0
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#define RTE_USART3_PIN_INIT LPUART3_InitPins
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#define RTE_USART3_PIN_DEINIT LPUART3_DeinitPins
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#define RTE_USART3_DMA_TX_CH 4
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#define RTE_USART3_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART3Tx
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#define RTE_USART3_DMA_TX_DMAMUX_BASE DMAMUX
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#define RTE_USART3_DMA_TX_DMA_BASE DMA0
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#define RTE_USART3_DMA_RX_CH 5
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#define RTE_USART3_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART3Rx
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#define RTE_USART3_DMA_RX_DMAMUX_BASE DMAMUX
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#define RTE_USART3_DMA_RX_DMA_BASE DMA0
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#define RTE_USART4_PIN_INIT LPUART4_InitPins
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#define RTE_USART4_PIN_DEINIT LPUART4_DeinitPins
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#define RTE_USART4_DMA_TX_CH 6
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#define RTE_USART4_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART4Tx
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#define RTE_USART4_DMA_TX_DMAMUX_BASE DMAMUX
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#define RTE_USART4_DMA_TX_DMA_BASE DMA0
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#define RTE_USART4_DMA_RX_CH 7
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#define RTE_USART4_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART4Rx
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#define RTE_USART4_DMA_RX_DMAMUX_BASE DMAMUX
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#define RTE_USART4_DMA_RX_DMA_BASE DMA0
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#define RTE_USART5_PIN_INIT LPUART5_InitPins
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#define RTE_USART5_PIN_DEINIT LPUART5_DeinitPins
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#define RTE_USART5_DMA_TX_CH 8
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#define RTE_USART5_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART5Tx
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#define RTE_USART5_DMA_TX_DMAMUX_BASE DMAMUX
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#define RTE_USART5_DMA_TX_DMA_BASE DMA0
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#define RTE_USART5_DMA_RX_CH 9
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#define RTE_USART5_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART5Rx
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#define RTE_USART5_DMA_RX_DMAMUX_BASE DMAMUX
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#define RTE_USART5_DMA_RX_DMA_BASE DMA0
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#define RTE_USART6_PIN_INIT LPUART6_InitPins
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#define RTE_USART6_PIN_DEINIT LPUART6_DeinitPins
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#define RTE_USART6_DMA_TX_CH 10
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#define RTE_USART6_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART6Tx
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#define RTE_USART6_DMA_TX_DMAMUX_BASE DMAMUX
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#define RTE_USART6_DMA_TX_DMA_BASE DMA0
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#define RTE_USART6_DMA_RX_CH 11
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#define RTE_USART6_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART6Rx
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#define RTE_USART6_DMA_RX_DMAMUX_BASE DMAMUX
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#define RTE_USART6_DMA_RX_DMA_BASE DMA0
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#define RTE_USART7_PIN_INIT LPUART7_InitPins
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#define RTE_USART7_PIN_DEINIT LPUART7_DeinitPins
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#define RTE_USART7_DMA_TX_CH 12
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#define RTE_USART7_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART7Tx
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#define RTE_USART7_DMA_TX_DMAMUX_BASE DMAMUX
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#define RTE_USART7_DMA_TX_DMA_BASE DMA0
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#define RTE_USART7_DMA_RX_CH 13
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#define RTE_USART7_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART7Rx
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#define RTE_USART7_DMA_RX_DMAMUX_BASE DMAMUX
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#define RTE_USART7_DMA_RX_DMA_BASE DMA0
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#define RTE_USART8_PIN_INIT LPUART8_InitPins
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#define RTE_USART8_PIN_DEINIT LPUART8_DeinitPins
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#define RTE_USART8_DMA_TX_CH 14
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#define RTE_USART8_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART8Tx
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#define RTE_USART8_DMA_TX_DMAMUX_BASE DMAMUX
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#define RTE_USART8_DMA_TX_DMA_BASE DMA0
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#define RTE_USART8_DMA_RX_CH 15
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#define RTE_USART8_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART8Rx
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#define RTE_USART8_DMA_RX_DMAMUX_BASE DMAMUX
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#define RTE_USART8_DMA_RX_DMA_BASE DMA0
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/* ENET configuration. */
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#define RTE_ENET 1
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#define RTE_ENET_PHY_ADDRESS 2
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#define RTE_ENET_MII 0
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#define RTE_ENET_RMII 1
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#endif /* _RTE_DEVICE_H */
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