437 lines
21 KiB
C
437 lines
21 KiB
C
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/*
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* Copyright 2017 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* How to setup clock using clock driver functions:
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*
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* 1. Call CLOCK_InitXXX() to configure corresponding SCG clock source.
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* Note: The clock could not be set when it is being used as system clock.
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* In default out of reset, the CPU is clocked from FIRC(IRC48M),
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* so before setting FIRC, change to use another avaliable clock source.
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*
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* 2. Call CLOCK_SetXtal0Freq() to set XTAL0 frequency based on board settings.
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*
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* 3. Call CLOCK_SetXxxModeSysClkConfig() to set SCG mode for Xxx run mode.
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* Wait until the system clock source is changed to target source.
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*
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* 4. If power mode change is needed, call SMC_SetPowerModeProtection() to allow
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* corresponding power mode and SMC_SetPowerModeXxx() to change to Xxx mode.
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* Supported run mode and clock restrictions could be found in Reference Manual.
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*/
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!GlobalInfo
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product: Clocks v3.0
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processor: RV32M1
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package_id: RV32M1
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mcu_data: ksdk2_0
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processor_version: 0.0.0
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board: RV32M1_VEGA
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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#include "fsl_msmc.h"
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#include "clock_config.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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#define SCG_LPFLL_DISABLE 0U /*!< LPFLL clock disabled */
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#define SCG_SOSC_DISABLE 0U /*!< System OSC disabled */
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/* System clock frequency. */
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extern uint32_t SystemCoreClock;
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/*******************************************************************************
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* Code
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******************************************************************************/
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#ifndef SDK_SECONDARY_CORE
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/*FUNCTION**********************************************************************
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*
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* Function Name : CLOCK_CONFIG_FircSafeConfig
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* Description : This function is used to safely configure FIRC clock.
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* In default out of reset, the CPU is clocked from FIRC(IRC48M).
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* Before setting FIRC, change to use SIRC as system clock,
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* then configure FIRC.
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* Param fircConfig : FIRC configuration.
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*
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*END**************************************************************************/
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static void CLOCK_CONFIG_FircSafeConfig(const scg_firc_config_t *fircConfig)
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{
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scg_sys_clk_config_t curConfig;
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const scg_sirc_config_t scgSircConfig = {.enableMode = kSCG_SircEnable,
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.div1 = kSCG_AsyncClkDisable,
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.div2 = kSCG_AsyncClkDivBy2,
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.range = kSCG_SircRangeHigh};
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scg_sys_clk_config_t sysClkSafeConfigSource = {
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.divSlow = kSCG_SysClkDivBy4, /* Slow clock divider. */
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.divCore = kSCG_SysClkDivBy1, /* Core clock divider. */
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.src = kSCG_SysClkSrcSirc /* System clock source. */
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};
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/* Init Sirc */
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CLOCK_InitSirc(&scgSircConfig);
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/* Change to use SIRC as system clock source to prepare to change FIRCCFG register */
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CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource);
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/* Wait for clock source switch finished */
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do
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{
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CLOCK_GetCurSysClkConfig(&curConfig);
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} while (curConfig.src != sysClkSafeConfigSource.src);
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/* Init Firc */
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CLOCK_InitFirc(fircConfig);
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}
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#endif
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/*******************************************************************************
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************************ BOARD_InitBootClocks function ************************
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******************************************************************************/
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void BOARD_InitBootClocks(void)
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{
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BOARD_BootClockRUN();
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}
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/*******************************************************************************
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********************** Configuration BOARD_BootClockRUN ***********************
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******************************************************************************/
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!Configuration
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name: BOARD_BootClockRUN
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called_from_default_init: true
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outputs:
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- {id: Bus_clock.outFreq, value: 48 MHz}
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- {id: Core_clock.outFreq, value: 48 MHz}
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- {id: FIRCDIV1_CLK.outFreq, value: 48 MHz}
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- {id: FIRCDIV2_CLK.outFreq, value: 48 MHz}
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- {id: FIRCDIV3_CLK.outFreq, value: 48 MHz}
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- {id: LPO_CLK.outFreq, value: 1 kHz}
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- {id: Platform_clock.outFreq, value: 48 MHz}
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- {id: SIRCDIV3_CLK.outFreq, value: 8 MHz}
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- {id: Slow_clock.outFreq, value: 24 MHz}
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- {id: System_clock.outFreq, value: 48 MHz}
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settings:
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- {id: SCG.FIRCDIV1.scale, value: '1', locked: true}
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- {id: SCG.FIRCDIV2.scale, value: '1', locked: true}
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- {id: SCG.FIRCDIV3.scale, value: '1', locked: true}
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- {id: SCG.LPFLLDIV1.scale, value: '1', locked: true}
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- {id: SCG.LPFLLDIV3.scale, value: '0', locked: true}
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- {id: SCG.SIRCDIV1.scale, value: '0', locked: true}
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- {id: SCG.SIRCDIV3.scale, value: '1', locked: true}
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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/*******************************************************************************
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* Variables for BOARD_BootClockRUN configuration
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******************************************************************************/
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const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockRUN =
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{
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.divSlow = kSCG_SysClkDivBy2, /* Slow Clock Divider: divided by 2 */
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.divBus = kSCG_SysClkDivBy1, /* Bus Clock Divider: divided by 1 */
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.divExt = kSCG_SysClkDivBy1, /* External Clock Divider: divided by 1 */
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.divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
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.src = kSCG_SysClkSrcFirc, /* Fast IRC is selected as System Clock Source */
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};
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const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockRUN =
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{
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.freq = 0U, /* System Oscillator frequency: 0Hz */
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.monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
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.enableMode = SCG_SOSC_DISABLE, /* System OSC disabled */
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.div1 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 1: Clock output is disabled */
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.div2 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 2: Clock output is disabled */
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.div3 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 3: Clock output is disabled */
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};
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const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN =
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{
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.enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,/* Enable SIRC clock, Enable SIRC in low power mode */
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.div1 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 1: Clock output is disabled */
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.div2 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 2: Clock output is disabled */
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.div3 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 3: divided by 1 */
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.range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
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};
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const scg_firc_config_t g_scgFircConfig_BOARD_BootClockRUN =
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{
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.enableMode = kSCG_FircEnable, /* Enable FIRC clock */
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.div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
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.div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
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.div3 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 3: divided by 1 */
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.range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
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.trimConfig = NULL,
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};
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const scg_lpfll_config_t g_scgLpFllConfig_BOARD_BootClockRUN =
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{
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.enableMode = SCG_LPFLL_DISABLE, /* LPFLL clock disabled */
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.div1 = kSCG_AsyncClkDivBy1, /* Low Power FLL Clock Divider 1: divided by 1 */
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.div2 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 2: Clock output is disabled */
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.div3 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 3: Clock output is disabled */
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.range = kSCG_LpFllRange48M, /* LPFLL is trimmed to 48MHz */
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.trimConfig = NULL,
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};
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/*******************************************************************************
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* Code for BOARD_BootClockRUN configuration
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******************************************************************************/
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void BOARD_BootClockRUN(void)
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{
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#ifndef SDK_SECONDARY_CORE
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scg_sys_clk_config_t curConfig;
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/* Init FIRC */
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CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockRUN);
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/* Set SCG to FIRC mode. */
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CLOCK_SetRunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockRUN);
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/* Wait for clock source switch finished */
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do
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{
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CLOCK_GetCurSysClkConfig(&curConfig);
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} while (curConfig.src != g_sysClkConfig_BOARD_BootClockRUN.src);
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/* Init SIRC */
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CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockRUN);
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/* Init LPFLL */
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CLOCK_InitLpFll(&g_scgLpFllConfig_BOARD_BootClockRUN);
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/* Set SystemCoreClock variable. */
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SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
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#endif
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}
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/*******************************************************************************
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********************* Configuration BOARD_BootClockHSRUN **********************
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******************************************************************************/
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!Configuration
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name: BOARD_BootClockHSRUN
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outputs:
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- {id: Bus_clock.outFreq, value: 72 MHz}
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- {id: Core_clock.outFreq, value: 72 MHz}
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- {id: FIRCDIV1_CLK.outFreq, value: 48 MHz}
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- {id: FIRCDIV2_CLK.outFreq, value: 48 MHz}
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- {id: FIRCDIV3_CLK.outFreq, value: 48 MHz}
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- {id: LPO_CLK.outFreq, value: 1 kHz}
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- {id: Platform_clock.outFreq, value: 72 MHz}
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- {id: SIRCDIV3_CLK.outFreq, value: 8 MHz}
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- {id: Slow_clock.outFreq, value: 8 MHz}
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- {id: System_clock.outFreq, value: 72 MHz}
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settings:
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- {id: SCGMode, value: LPFLL}
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- {id: powerMode, value: HSRUN}
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- {id: SCG.DIVCORE.scale, value: '1', locked: true}
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- {id: SCG.DIVSLOW.scale, value: '9'}
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- {id: SCG.FIRCDIV1.scale, value: '1', locked: true}
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- {id: SCG.FIRCDIV2.scale, value: '1', locked: true}
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- {id: SCG.FIRCDIV3.scale, value: '1', locked: true}
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- {id: SCG.LPFLLDIV1.scale, value: '0', locked: true}
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- {id: SCG.LPFLL_mul.scale, value: '36', locked: true}
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- {id: SCG.SCSSEL.sel, value: SCG.LPFLL}
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- {id: SCG.SIRCDIV3.scale, value: '1', locked: true}
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- {id: SCG.TRIMDIV.scale, value: '24'}
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- {id: SCG.TRIMSRCSEL.sel, value: SCG.FIRC}
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- {id: 'SCG::RCCR[SCS].bitField', value: '5'}
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- {id: SCG_LPFLLCSR_LPFLLEN_CFG, value: Enabled}
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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/*******************************************************************************
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* Variables for BOARD_BootClockHSRUN configuration
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******************************************************************************/
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const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockHSRUN =
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{
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.divSlow = kSCG_SysClkDivBy9, /* Slow Clock Divider: divided by 9 */
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.divBus = kSCG_SysClkDivBy1, /* Bus Clock Divider: divided by 1 */
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.divExt = kSCG_SysClkDivBy1, /* External Clock Divider: divided by 1 */
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.divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
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.src = kSCG_SysClkSrcLpFll, /* Low power FLL is selected as System Clock Source */
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};
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const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockHSRUN =
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{
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.freq = 0U, /* System Oscillator frequency: 0Hz */
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.monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
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.enableMode = SCG_SOSC_DISABLE, /* System OSC disabled */
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.div1 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 1: Clock output is disabled */
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.div2 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 2: Clock output is disabled */
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.div3 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 3: Clock output is disabled */
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};
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const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockHSRUN =
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{
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.enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,/* Enable SIRC clock, Enable SIRC in low power mode */
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.div1 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 1: Clock output is disabled */
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.div2 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 2: Clock output is disabled */
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.div3 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 3: divided by 1 */
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.range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
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};
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const scg_firc_config_t g_scgFircConfig_BOARD_BootClockHSRUN =
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{
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.enableMode = kSCG_FircEnable, /* Enable FIRC clock */
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.div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
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.div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
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.div3 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 3: divided by 1 */
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.range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
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.trimConfig = NULL,
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};
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const scg_lpfll_config_t g_scgLpFllConfig_BOARD_BootClockHSRUN =
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{
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.enableMode = kSCG_LpFllEnable, /* Enable LPFLL clock */
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.div1 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 1: Clock output is disabled */
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.div2 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 2: Clock output is disabled */
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.div3 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 3: Clock output is disabled */
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.range = kSCG_LpFllRange72M, /* LPFLL is trimmed to 72MHz */
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.trimConfig = NULL,
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};
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/*******************************************************************************
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* Code for BOARD_BootClockHSRUN configuration
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******************************************************************************/
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void BOARD_BootClockHSRUN(void)
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{
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#ifndef SDK_SECONDARY_CORE
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scg_sys_clk_config_t curConfig;
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/* Init FIRC */
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CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockHSRUN);
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/* Init LPFLL */
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CLOCK_InitLpFll(&g_scgLpFllConfig_BOARD_BootClockHSRUN);
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#if defined(CPU_RV32M1_cm4) || defined(CPU_RV32M1_ri5cy)
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/* Set HSRUN power mode */
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SMC_SetPowerModeProtection(SMC0, kSMC_AllowPowerModeAll);
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SMC_SetPowerModeHsrun(SMC0);
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while (SMC_GetPowerModeState(SMC0) != kSMC_PowerStateHsrun)
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{
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}
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||
|
|
#elif defined(CPU_RV32M1_cm0plus) || defined(CPU_RV32M1_zero_riscy)
|
||
|
|
SMC_SetPowerModeProtection(SMC1, kSMC_AllowPowerModeAll);
|
||
|
|
SMC_SetPowerModeHsrun(SMC1);
|
||
|
|
while (SMC_GetPowerModeState(SMC1) != kSMC_PowerStateHsrun)
|
||
|
|
{
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
/* Set SCG to LPFLL mode. */
|
||
|
|
CLOCK_SetHsrunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockHSRUN);
|
||
|
|
/* Wait for clock source switch finished */
|
||
|
|
do
|
||
|
|
{
|
||
|
|
CLOCK_GetCurSysClkConfig(&curConfig);
|
||
|
|
} while (curConfig.src != g_sysClkConfig_BOARD_BootClockHSRUN.src);
|
||
|
|
/* Init SIRC */
|
||
|
|
CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockHSRUN);
|
||
|
|
/* Set SystemCoreClock variable. */
|
||
|
|
SystemCoreClock = BOARD_BOOTCLOCKHSRUN_CORE_CLOCK;
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
/*******************************************************************************
|
||
|
|
********************* Configuration BOARD_BootClockVLPR ***********************
|
||
|
|
******************************************************************************/
|
||
|
|
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||
|
|
!!Configuration
|
||
|
|
name: BOARD_BootClockVLPR
|
||
|
|
outputs:
|
||
|
|
- {id: Bus_clock.outFreq, value: 2 MHz}
|
||
|
|
- {id: Core_clock.outFreq, value: 4 MHz}
|
||
|
|
- {id: LPO_CLK.outFreq, value: 1 kHz}
|
||
|
|
- {id: Platform_clock.outFreq, value: 4 MHz}
|
||
|
|
- {id: SIRCDIV1_CLK.outFreq, value: 8 MHz}
|
||
|
|
- {id: SIRCDIV2_CLK.outFreq, value: 8 MHz}
|
||
|
|
- {id: SIRCDIV3_CLK.outFreq, value: 8 MHz}
|
||
|
|
- {id: Slow_clock.outFreq, value: 4000/9 kHz}
|
||
|
|
- {id: System_clock.outFreq, value: 4 MHz}
|
||
|
|
settings:
|
||
|
|
- {id: SCGMode, value: SIRC}
|
||
|
|
- {id: powerMode, value: VLPR}
|
||
|
|
- {id: SCG.DIVBUS.scale, value: '2', locked: true}
|
||
|
|
- {id: SCG.DIVCORE.scale, value: '2', locked: true}
|
||
|
|
- {id: SCG.DIVSLOW.scale, value: '9'}
|
||
|
|
- {id: SCG.FIRCDIV1.scale, value: '1'}
|
||
|
|
- {id: SCG.SCSSEL.sel, value: SCG.SIRC}
|
||
|
|
- {id: SCG.SIRCDIV1.scale, value: '1', locked: true}
|
||
|
|
- {id: SCG.SIRCDIV2.scale, value: '1', locked: true}
|
||
|
|
- {id: SCG.SIRCDIV3.scale, value: '1', locked: true}
|
||
|
|
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||
|
|
|
||
|
|
/*******************************************************************************
|
||
|
|
* Variables for BOARD_BootClockVLPR configuration
|
||
|
|
******************************************************************************/
|
||
|
|
const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockVLPR =
|
||
|
|
{
|
||
|
|
.divSlow = kSCG_SysClkDivBy9, /* Slow Clock Divider: divided by 9 */
|
||
|
|
.divBus = kSCG_SysClkDivBy2, /* Bus Clock Divider: divided by 2 */
|
||
|
|
.divExt = kSCG_SysClkDivBy1, /* External Clock Divider: divided by 1 */
|
||
|
|
.divCore = kSCG_SysClkDivBy2, /* Core Clock Divider: divided by 2 */
|
||
|
|
.src = kSCG_SysClkSrcSirc, /* Slow IRC is selected as System Clock Source */
|
||
|
|
};
|
||
|
|
const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockVLPR =
|
||
|
|
{
|
||
|
|
.freq = 0U, /* System Oscillator frequency: 0Hz */
|
||
|
|
.monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
|
||
|
|
.enableMode = SCG_SOSC_DISABLE, /* System OSC disabled */
|
||
|
|
.div1 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 1: Clock output is disabled */
|
||
|
|
.div2 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 2: Clock output is disabled */
|
||
|
|
.div3 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 3: Clock output is disabled */
|
||
|
|
};
|
||
|
|
const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR =
|
||
|
|
{
|
||
|
|
.enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,/* Enable SIRC clock, Enable SIRC in low power mode */
|
||
|
|
.div1 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 1: divided by 1 */
|
||
|
|
.div2 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 2: divided by 1 */
|
||
|
|
.div3 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 3: divided by 1 */
|
||
|
|
.range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
|
||
|
|
};
|
||
|
|
const scg_firc_config_t g_scgFircConfig_BOARD_BootClockVLPR =
|
||
|
|
{
|
||
|
|
.enableMode = kSCG_FircEnable, /* Enable FIRC clock */
|
||
|
|
.div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
|
||
|
|
.div2 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 2: Clock output is disabled */
|
||
|
|
.div3 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 3: Clock output is disabled */
|
||
|
|
.range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
|
||
|
|
.trimConfig = NULL,
|
||
|
|
};
|
||
|
|
const scg_lpfll_config_t g_scgLpFllConfig_BOARD_BootClockVLPR =
|
||
|
|
{
|
||
|
|
.enableMode = SCG_LPFLL_DISABLE, /* LPFLL clock disabled */
|
||
|
|
.div1 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 1: Clock output is disabled */
|
||
|
|
.div2 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 2: Clock output is disabled */
|
||
|
|
.div3 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 3: Clock output is disabled */
|
||
|
|
.range = kSCG_LpFllRange48M, /* LPFLL is trimmed to 48MHz */
|
||
|
|
.trimConfig = NULL,
|
||
|
|
};
|
||
|
|
/*******************************************************************************
|
||
|
|
* Code for BOARD_BootClockVLPR configuration
|
||
|
|
******************************************************************************/
|
||
|
|
void BOARD_BootClockVLPR(void)
|
||
|
|
{
|
||
|
|
#ifndef SDK_SECONDARY_CORE
|
||
|
|
scg_sys_clk_config_t curConfig;
|
||
|
|
|
||
|
|
/* Init SIRC */
|
||
|
|
CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockVLPR);
|
||
|
|
/* Set SCG to SIRC mode. */
|
||
|
|
CLOCK_SetVlprModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockVLPR);
|
||
|
|
/* Init FIRC */
|
||
|
|
CLOCK_InitFirc(&g_scgFircConfig_BOARD_BootClockVLPR);
|
||
|
|
/* Init LPFLL */
|
||
|
|
CLOCK_InitLpFll(&g_scgLpFllConfig_BOARD_BootClockVLPR);
|
||
|
|
#if defined(CPU_RV32M1_cm4) || defined(CPU_RV32M1_ri5cy)
|
||
|
|
/* Set VLPR power mode. */
|
||
|
|
SMC_SetPowerModeProtection(SMC0, kSMC_AllowPowerModeAll);
|
||
|
|
SMC_SetPowerModeVlpr(SMC0);
|
||
|
|
while (SMC_GetPowerModeState(SMC0) != kSMC_PowerStateVlpr)
|
||
|
|
{
|
||
|
|
}
|
||
|
|
#elif defined(CPU_RV32M1_cm0plus) || defined(CPU_RV32M1_zero_riscy)
|
||
|
|
/* Set VLPR power mode. */
|
||
|
|
SMC_SetPowerModeProtection(SMC1, kSMC_AllowPowerModeAll);
|
||
|
|
SMC_SetPowerModeVlpr(SMC1);
|
||
|
|
while (SMC_GetPowerModeState(SMC1) != kSMC_PowerStateVlpr)
|
||
|
|
{
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
/* Wait for clock source switch finished */
|
||
|
|
do
|
||
|
|
{
|
||
|
|
CLOCK_GetCurSysClkConfig(&curConfig);
|
||
|
|
} while (curConfig.src != g_sysClkConfig_BOARD_BootClockVLPR.src);
|
||
|
|
/* Set SystemCoreClock variable. */
|
||
|
|
SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|