454 lines
12 KiB
C
454 lines
12 KiB
C
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/*
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* File : interrupt.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006, RT-Thread Development Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Change Logs:
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* Date Author Notes
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* 2011-01-13 weety first version
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*/
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#include <rthw.h>
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#include "at91sam9g45.h"
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#include "interrupt.h"
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#define AIC_IRQS 32
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#define MAX_HANDLERS (AIC_IRQS + PIN_IRQS)
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extern rt_uint32_t rt_interrupt_nest;
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/* exception and interrupt handler table */
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struct rt_irq_desc irq_desc[MAX_HANDLERS];
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rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
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rt_uint32_t rt_thread_switch_interrupt_flag;
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/* --------------------------------------------------------------------
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* Interrupt initialization
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* -------------------------------------------------------------------- */
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rt_uint32_t at91_extern_irq;
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#define is_extern_irq(irq) ((1 << (irq)) & at91_extern_irq)
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/*
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* The default interrupt priority levels (0 = lowest, 7 = highest).
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*/
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static rt_uint32_t at91sam9g45_default_irq_priority[MAX_HANDLERS] = {
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7, /* Advanced Interrupt Controller - FIQ */
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7, /* System Controller Interrupt */
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1, /* Parallel I/O Controller A, */
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1, /* Parallel I/O Controller B */
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1, /* Parallel I/O Controller C */
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0, /* Parallel I/O Controller D/E */
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5, /* True Random Number Generator */
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5, /* USART 0 */
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5, /* USART 1 */
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0, /* USART 2 */
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2, /* USART 3 */
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6, /* High Speed Multimedia Card Interface 0 */
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5, /* Two-Wire Interface 0 */
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5, /* Two-Wire Interface 1 */
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5, /* Serial Peripheral Interface */
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0, /* Serial Peripheral Interface */
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0, /* Synchronous Serial Controller 0 */
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0, /* Synchronous Serial Controller 1 */
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0, /* Timer Counter 0,1,2,3,4,5 */
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0, /* Pulse Width Modulation Controller */
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2, /* Touch Screen ADC Controller */
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3, /* DMA Controller */
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0, /* USB Host High Speed */
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5, /* LCD Controller */
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5, /* AC97 Controller */
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5, /* Ethernet MAC */
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0, /* Image Sensor Interface */
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0, /* USB Device High Speed */
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0, /* N/A */
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0, /* High Speed Multimedia Card Interface 1 */
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0, /* Reserved */
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0, /* Advanced Interrupt Controller - IRQ */
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};
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/**
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* @addtogroup AT91SAM9G45
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*/
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/*@{*/
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void rt_hw_interrupt_mask(int irq);
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void rt_hw_interrupt_umask(int irq);
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rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector, void *param)
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{
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rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
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return RT_NULL;
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}
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rt_isr_handler_t at91_gpio_irq_handle(rt_uint32_t bank, void *param)
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{
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rt_uint32_t isr, irq_n;
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AT91PS_PIO pio;
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void *parameter;
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switch (bank)
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{
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case 0: pio = AT91C_BASE_PIOA; break;
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case 1: pio = AT91C_BASE_PIOB; break;
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case 2: pio = AT91C_BASE_PIOC; break;
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case 3: pio = AT91C_BASE_PIOD; break;
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case 4: pio = AT91C_BASE_PIOE; break;
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default: return RT_NULL;
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}
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irq_n = AIC_IRQS + 32*bank;
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isr = readl(pio->PIO_ISR);
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isr &= readl(pio->PIO_IMR);
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while (isr)
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{
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if (isr & 1)
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{
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parameter = irq_desc[irq_n].param;
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irq_desc[irq_n].handler(irq_n, parameter);
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}
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isr >>= 1;
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irq_n++;
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}
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return RT_NULL;
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}
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unsigned int SpuriousCount = 0;
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static void DefaultSpuriousHandler( void )
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{
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SpuriousCount++;
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rt_kprintf("Spurious interrupt %d occured!!!\n", SpuriousCount);
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return ;
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}
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static void DefaultFiqHandler(void)
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{
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rt_kprintf("Unhandled FIQ occured!!!\n");
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while (1);
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}
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static void DefaultIrqHandler(void)
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{
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rt_kprintf("Unhandled IRQ %d occured!!!\n", AT91C_BASE_AIC->AIC_ISR);
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while (1);
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}
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/*
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* Initialize the AIC interrupt controller.
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*/
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void at91_aic_init(rt_uint32_t *priority)
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{
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rt_uint32_t i;
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/*
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* The IVR is used by macro get_irqnr_and_base to read and verify.
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* The irq number is NR_AIC_IRQS when a spurious interrupt has occurred.
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*/
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AT91C_BASE_AIC->AIC_SVR[0] = (rt_uint32_t)DefaultFiqHandler;
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for (i = 1; i < AIC_IRQS; i++) {
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/* Put irq number in Source Vector Register: */
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AT91C_BASE_AIC->AIC_SVR[i] = (rt_uint32_t)DefaultIrqHandler; // no-used
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/* Active Low interrupt, with the specified priority */
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AT91C_BASE_AIC->AIC_SMR[i] = AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE | priority[i];
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//AT91C_AIC_SRCTYPE_FALLING
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}
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/*
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* Spurious Interrupt ID in Spurious Vector Register is NR_AIC_IRQS
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* When there is no current interrupt, the IRQ Vector Register reads the value stored in AIC_SPU
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*/
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AT91C_BASE_AIC->AIC_SPU = (rt_uint32_t)DefaultSpuriousHandler;
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/* Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ */
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for (i = 0; i < 8; i++)
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AT91C_BASE_AIC->AIC_EOICR = 0;
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/* No debugging in AIC: Debug (Protect) Control Register */
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AT91C_BASE_AIC->AIC_DCR = 0;
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/* Disable and clear all interrupts initially */
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AT91C_BASE_AIC->AIC_IDCR = 0xFFFFFFFF;
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AT91C_BASE_AIC->AIC_ICCR = 0xFFFFFFFF;
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}
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static void at91_gpio_irq_init()
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{
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int i, idx;
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char *name[] = {"PIOA", "PIOB", "PIOC", "PIODE"};
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rt_uint32_t aic_pids[] = { AT91C_ID_PIOA, AT91C_ID_PIOB, AT91C_ID_PIOC, AT91C_ID_PIOD_E };
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AT91C_BASE_PIOA->PIO_IDR = 0xffffffff;
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AT91C_BASE_PIOB->PIO_IDR = 0xffffffff;
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AT91C_BASE_PIOC->PIO_IDR = 0xffffffff;
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AT91C_BASE_PIOD->PIO_IDR = 0xffffffff;
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AT91C_BASE_PIOE->PIO_IDR = 0xffffffff;
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for (i = 0; i < 4; i++)
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{
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idx = aic_pids[i];
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irq_desc[idx].handler = (rt_isr_handler_t)at91_gpio_irq_handle;
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irq_desc[idx].param = RT_NULL;
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#ifdef RT_USING_INTERRUPT_INFO
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rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, name[i]);
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irq_desc[idx].counter = 0;
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#endif
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rt_hw_interrupt_umask(idx);
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}
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}
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/**
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* This function will initialize hardware interrupt
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*/
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void rt_hw_interrupt_init(void)
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{
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register rt_uint32_t idx;
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rt_uint32_t *priority = at91sam9g45_default_irq_priority;
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at91_extern_irq = (1UL << AT91C_ID_IRQ0);
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/* Initialize the AIC interrupt controller */
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at91_aic_init(priority);
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/* init exceptions table */
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for(idx=0; idx < MAX_HANDLERS; idx++)
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{
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irq_desc[idx].handler = (rt_isr_handler_t)rt_hw_interrupt_handle;
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irq_desc[idx].param = RT_NULL;
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#ifdef RT_USING_INTERRUPT_INFO
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rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, "default");
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irq_desc[idx].counter = 0;
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#endif
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}
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at91_gpio_irq_init();
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/* init interrupt nest, and context in thread sp */
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rt_interrupt_nest = 0;
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rt_interrupt_from_thread = 0;
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rt_interrupt_to_thread = 0;
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rt_thread_switch_interrupt_flag = 0;
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}
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static void at91_gpio_irq_mask(int irq)
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{
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rt_uint32_t pin, bank;
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AT91PS_PIO pio;
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bank = (irq - AIC_IRQS)>>5;
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switch (bank)
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{
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case 0: pio = AT91C_BASE_PIOA; break;
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case 1: pio = AT91C_BASE_PIOB; break;
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case 2: pio = AT91C_BASE_PIOC; break;
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case 3: pio = AT91C_BASE_PIOD; break;
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case 4: pio = AT91C_BASE_PIOE; break;
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default: return;
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}
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pin = 1 << ((irq - AIC_IRQS) & 31);
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pio->PIO_IDR = pin;
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}
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/**
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* This function will mask a interrupt.
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* @param irq the interrupt number
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*/
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void rt_hw_interrupt_mask(int irq)
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{
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if (irq >= AIC_IRQS)
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{
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at91_gpio_irq_mask(irq);
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}
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else
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{
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/* Disable interrupt on AIC */
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AT91C_BASE_AIC->AIC_IDCR = 1 << irq;
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}
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}
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static void at91_gpio_irq_umask(int irq)
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{
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rt_uint32_t pin, bank;
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AT91PS_PIO pio;
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bank = (irq - AIC_IRQS)>>5;
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switch (bank)
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{
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case 0: pio = AT91C_BASE_PIOA; break;
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case 1: pio = AT91C_BASE_PIOB; break;
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case 2: pio = AT91C_BASE_PIOC; break;
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case 3: pio = AT91C_BASE_PIOD; break;
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case 4: pio = AT91C_BASE_PIOE; break;
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default: return;
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}
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pin = 1 << ((irq - AIC_IRQS) & 31);
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pio->PIO_IER = pin;
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}
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/**
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* This function will un-mask a interrupt.
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* @param vector the interrupt number
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*/
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void rt_hw_interrupt_umask(int irq)
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{
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if (irq >= AIC_IRQS)
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{
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at91_gpio_irq_umask(irq);
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}
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else
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{
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/* Enable interrupt on AIC */
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AT91C_BASE_AIC->AIC_IECR = 1 << irq;
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}
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}
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/**
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* This function will install a interrupt service routine to a interrupt.
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* @param vector the interrupt number
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* @param handler the interrupt service routine to be installed
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* @param param the interrupt service function parameter
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* @param name the interrupt name
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* @return old handler
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*/
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rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
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void *param, char *name)
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{
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rt_isr_handler_t old_handler = RT_NULL;
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if (vector < MAX_HANDLERS)
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{
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old_handler = irq_desc[vector].handler;
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if (handler != RT_NULL)
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{
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irq_desc[vector].handler = (rt_isr_handler_t)handler;
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irq_desc[vector].param = param;
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#ifdef RT_USING_INTERRUPT_INFO
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rt_snprintf(irq_desc[vector].name, RT_NAME_MAX - 1, "%s", name);
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irq_desc[vector].counter = 0;
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#endif
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}
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}
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return old_handler;
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}
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/*@}*/
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/*
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static int at91_aic_set_type(unsigned irq, unsigned type)
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{
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unsigned int smr, srctype;
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switch (type) {
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case AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL:
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srctype = AT91C_AIC_SRCTYPE_HIGH;
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break;
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case AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE:
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srctype = AT91C_AIC_SRCTYPE_RISING;
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break;
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case AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE:
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|
// only supported on external interrupts
|
||
|
|
if ((irq == AT91C_ID_FIQ) || is_extern_irq(irq))
|
||
|
|
srctype = AT91C_AIC_SRCTYPE_LOW;
|
||
|
|
else
|
||
|
|
return -1;
|
||
|
|
break;
|
||
|
|
case AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED:
|
||
|
|
// only supported on external interrupts
|
||
|
|
if ((irq == AT91C_ID_FIQ) || is_extern_irq(irq))
|
||
|
|
srctype = AT91C_AIC_SRCTYPE_FALLING;
|
||
|
|
else
|
||
|
|
return -1;
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
return -1;
|
||
|
|
}
|
||
|
|
|
||
|
|
smr = readl(AT91C_AIC_SMR(irq)) & ~AT91C_AIC_SRCTYPE;
|
||
|
|
AT91C_BASE_AIC->AIC_SMR[irq] = smr | srctype;
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
*/
|
||
|
|
rt_uint32_t rt_hw_interrupt_get_active(rt_uint32_t fiq_irq)
|
||
|
|
{
|
||
|
|
|
||
|
|
//volatile rt_uint32_t irqstat;
|
||
|
|
rt_uint32_t id;
|
||
|
|
if (fiq_irq == INT_FIQ)
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
//IRQ
|
||
|
|
/* AIC need this dummy read */
|
||
|
|
readl(AT91C_AIC_IVR);
|
||
|
|
/* clear pending register */
|
||
|
|
id = readl(AT91C_AIC_ISR);
|
||
|
|
|
||
|
|
return id;
|
||
|
|
}
|
||
|
|
|
||
|
|
void rt_hw_interrupt_ack(rt_uint32_t fiq_irq, rt_uint32_t id)
|
||
|
|
{
|
||
|
|
/* new FIQ generation */
|
||
|
|
if (fiq_irq == INT_FIQ)
|
||
|
|
return;
|
||
|
|
|
||
|
|
/* new IRQ generation */
|
||
|
|
// EIOCR must be write any value after interrupt,
|
||
|
|
// or else can't response next interrupt
|
||
|
|
AT91C_BASE_AIC->AIC_EOICR = 0x0;
|
||
|
|
}
|
||
|
|
|
||
|
|
#ifdef RT_USING_FINSH
|
||
|
|
#ifdef RT_USING_INTERRUPT_INFO
|
||
|
|
void list_irq(void)
|
||
|
|
{
|
||
|
|
int irq;
|
||
|
|
|
||
|
|
rt_kprintf("number\tcount\tname\n");
|
||
|
|
for (irq = 0; irq < MAX_HANDLERS; irq++)
|
||
|
|
{
|
||
|
|
if (rt_strncmp(irq_desc[irq].name, "default", sizeof("default")))
|
||
|
|
{
|
||
|
|
rt_kprintf("%02ld: %10ld %s\n", irq, irq_desc[irq].counter, irq_desc[irq].name);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
#include <finsh.h>
|
||
|
|
FINSH_FUNCTION_EXPORT(list_irq, list system irq);
|
||
|
|
|
||
|
|
#ifdef FINSH_USING_MSH
|
||
|
|
int cmd_list_irq(int argc, char** argv)
|
||
|
|
{
|
||
|
|
list_irq();
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
FINSH_FUNCTION_EXPORT_ALIAS(cmd_list_irq, __cmd_list_irq, list system irq.);
|
||
|
|
|
||
|
|
#endif
|
||
|
|
#endif
|
||
|
|
#endif
|
||
|
|
|
||
|
|
|