320 lines
11 KiB
C
320 lines
11 KiB
C
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/*
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* @ : Copyright (c) 2021 Phytium Information Technology, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0.
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*
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* @Date: 2021-01-22 16:30:56
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* @LastEditTime: 2021-05-24 14:35:53
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* @LastEditors: Please set LastEditors
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* @Description: In User Settings Edit
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* @FilePath: \project_freertos\devices\ft2004\bsp\core\ft_asm.h
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*/
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#ifndef FT_AARCH32_ASM_H
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#define FT_AARCH32_ASM_H
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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#include "ft_types.h"
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#define __ASM __asm
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#define __STRINGIFY(x) #x
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/* C语言实现MCR指令 */
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#define __MCR(coproc, opcode_1, src, CRn, CRm, opcode_2) \
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__ASM volatile("MCR " __STRINGIFY(p##coproc) ", " __STRINGIFY(opcode_1) ", " \
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"%0, " __STRINGIFY(c##CRn) ", " __STRINGIFY(c##CRm) ", " __STRINGIFY(opcode_2) \
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: \
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: "r"(src) \
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: "memory");
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/* C语言实现MRC指令 */
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#define __MRC(coproc, opcode_1, CRn, CRm, opcode_2) \
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({ \
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u32 __dst; \
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__ASM volatile("MRC " __STRINGIFY(p##coproc) ", " __STRINGIFY(opcode_1) ", " \
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"%0, " __STRINGIFY(c##CRn) ", " __STRINGIFY(c##CRm) ", " __STRINGIFY(opcode_2) \
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: "=r"(__dst)::"memory"); \
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__dst; \
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})
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__attribute__((always_inline)) __STATIC_INLINE u32 __get_VBAR(void)
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{
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return __MRC(15, 0, 12, 0, 0);
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}
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__attribute__((always_inline)) __STATIC_INLINE void __set_VBAR(u32 vbar)
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{
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__MCR(15, 0, vbar, 12, 0, 0);
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}
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__attribute__((always_inline)) __STATIC_INLINE void sys_icc_igrpen0_set(u32 value)
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{
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__MCR(15, 0, value, 12, 12, 6);
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}
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__attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_igrpen0_get(void)
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{
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return __MRC(15, 0, 12, 12, 6);
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}
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__attribute__((always_inline)) __STATIC_INLINE void sys_icc_igrpen1_set(u32 value)
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{
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__MCR(15, 0, value, 12, 12, 7);
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}
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__attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_igrpen1_get(void)
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{
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return __MRC(15, 0, 12, 12, 7);
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}
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__attribute__((always_inline)) __STATIC_INLINE void sys_icc_ctlr_set(u32 value)
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{
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__MCR(15, 0, value, 12, 12, 4);
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}
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__attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_ctlr_get(void)
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{
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return __MRC(15, 0, 12, 12, 4);
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}
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__attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_hppir0_get(void)
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{
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return __MRC(15, 0, 12, 8, 2);
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}
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__attribute__((always_inline)) __STATIC_INLINE void sys_icc_bpr_set(u32 value)
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{
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__MCR(15, 0, value, 12, 12, 3);
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}
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__attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_bpr_get(void)
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{
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return __MRC(15, 0, 12, 12, 3);
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}
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__attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_hppir1_get(void)
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{
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return __MRC(15, 0, 12, 12, 2);
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}
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__attribute__((always_inline)) __STATIC_INLINE void sys_icc_eoir0_set(u32 value)
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{
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__MCR(15, 0, value, 12, 8, 1);
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}
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__attribute__((always_inline)) __STATIC_INLINE void sys_icc_eoir1_set(u32 value)
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{
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__MCR(15, 0, value, 12, 12, 1);
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}
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__attribute__((always_inline)) __STATIC_INLINE void sys_icc_pmr_set(u32 value)
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{
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__MCR(15, 0, value, 4, 6, 0);
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}
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__attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_pmr_get(void)
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{
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return __MRC(15, 0, 4, 6, 0);
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}
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__attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_iar1_get(void)
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{
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return __MRC(15, 0, 12, 12, 0);
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}
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__attribute__((always_inline)) __STATIC_INLINE void sys_icc_sre_set(u32 value)
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{
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__MCR(15, 0, value, 12, 12, 5);
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}
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__attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_sre_get(void)
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{
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return __MRC(15, 0, 12, 12, 5);
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}
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__attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_rpr_get(void)
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{
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return __MRC(15, 0, 12, 11, 3);
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}
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/* Generic Timer registers */
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/**
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* @name: arm_aarch32_cntfrq_get
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* @msg: This register is provided so that software can discover the frequency of the system counter.
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* @return {__STATIC_INLINEu32}: frequency of the system counter
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*/
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__attribute__((always_inline)) __STATIC_INLINE u32 arm_aarch32_cntfrq_get(void)
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{
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return __MRC(15, 0, 14, 0, 0);
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}
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/**
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* @name: arm_aarch32_cnthv_tval_get
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* @msg: Provides AArch32 access to the timer value for the EL2 virtual timer.
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* @return {__STATIC_INLINEu32}: EL2 virtual timer Cnt.
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*/
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__attribute__((always_inline)) __STATIC_INLINE u32 arm_aarch32_cnthv_tval_get(void)
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{
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return __MRC(15, 0, 14, 3, 0);
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}
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/**
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* @name: arm_aarch32_cnthv_ctl_set
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* @msg: Provides AArch32 access to the control register for the EL2 virtual timer.
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* @in param {u32}: RegValue;ENABLE: bit [0] 0 Timer disabled,1 Timer enabled.
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* IMASK,bit [1]: 0 Timer interrupt is not masked by the IMASK bit. 1 Timer interrupt is masked by the IMASK bit.
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* ISTATUS, bit [2]: 0 Timer condition is not met. 1 Timer condition is met. rea-only
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*/
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__attribute__((always_inline)) __STATIC_INLINE void arm_aarch32_cnthv_ctl_set(u32 RegValue)
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{
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__MCR(15, 0, RegValue, 14, 3, 1);
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}
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/**
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* @name: arm_aarch32_cnthv_ctl_get
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* @msg: Provides AArch32 access to the control register for the EL2 virtual timer.
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* @return {__STATIC_INLINEu32}: RegValue;ENABLE: bit [0] 0 Timer disabled,1 Timer enabled.
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* IMASK,bit [1]: 0 Timer interrupt is not masked by the IMASK bit. 1 Timer interrupt is masked by the IMASK bit.
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* ISTATUS, bit [2]: 0 Timer condition is not met. 1 Timer condition is met. read-only
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*/
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__attribute__((always_inline)) __STATIC_INLINE u32 arm_aarch32_cnthv_ctl_get(void)
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{
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return __MRC(15, 0, 14, 3, 1);
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}
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/**
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* @name: arm_aarch32_cnthv_tval_set
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* @msg: Provides AArch32 access to the timer value for the EL2 virtual timer.
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* @in param {u32}: TimerValue, bits [31:0] The TimerValue view of the EL2 virtual timer.
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*/
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__attribute__((always_inline)) __STATIC_INLINE void arm_aarch32_cnthv_tval_set(u32 RegValue)
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{
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__MCR(15, 0, RegValue, 14, 3, 0);
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}
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/**
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* @name: arm_aarch32_cntvct_get
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* @msg: Read the register that holds the 64-bit virtual count value. The virtual count value is equal to the physical count value visible in CNTPCT minus the virtual offset visible in CNTVOFF.
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* @return {__STATIC_INLINEu64}Bits [63:0] Virtual count value.
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*/
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__attribute__((always_inline)) __STATIC_INLINE u64 arm_aarch32_cntvct_get(void)
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{
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/* "r0" --- low,
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"r1" --- hi
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*/
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u32 low;
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u32 hi;
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__asm__ volatile(
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".word 0xec510f1e \n" /* mrrc p15, 1, r0, r1, c14 */
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"mov %0, r0 \n"
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"mov %1, r1 \n"
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: "=&r"(low), "=&r"(hi));
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return (((u64)hi) << 32) | low;
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}
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/* physical */
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/**
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* @name: arm_aarch32_cntp_tval_get
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* @msg: Read the register that holds the timer value for the EL1 physical timer.
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* @return {__STATIC_INLINEu32}: TimerValue, bits [31:0] The TimerValue view of the EL1 physical timer.
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*/
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__attribute__((always_inline)) __STATIC_INLINE u32 arm_aarch32_cntp_tval_get(void)
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{
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return __MRC(15, 0, 14, 2, 0);
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}
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/**
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* @name: arm_aarch32_cntp_tval_set
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* @msg: write the register that control register for the EL1 physical timer.
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* @in param {u32}: TimerValue, bits [31:0] The TimerValue view of the EL1 physical timer.
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*/
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__attribute__((always_inline)) __STATIC_INLINE void arm_aarch32_cntp_tval_set(u32 RegValue)
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{
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__MCR(15, 0, RegValue, 14, 2, 0);
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}
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/**
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* @name: arm_aarch32_cntp_ctl_set
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* @msg: write the register that control register for the EL1 physical timer.
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* @in param {u32}: ENABLE, bit[0] Enables the timer ; IMASK, bit [1] Timer interrupt mask bit; ISTATUS, bit [2] The status of the timer.
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*/
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__attribute__((always_inline)) __STATIC_INLINE void arm_aarch32_cntp_ctl_set(u32 RegValue)
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{
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__MCR(15, 0, RegValue, 14, 2, 1);
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}
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/**
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* @name: arm_aarch32_cntp_ctl_get
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* @msg: Read the register that control register for the EL1 physical timer.
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* @return {__STATIC_INLINEu32}: ENABLE, bit[0] Enables the timer ; IMASK, bit [1] Timer interrupt mask bit; ISTATUS, bit [2] The status of the timer.
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*/
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__attribute__((always_inline)) __STATIC_INLINE u32 arm_aarch32_cntp_ctl_get(void)
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{
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return __MRC(15, 0, 14, 2, 1);
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}
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/**
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* @name: arm_aarch32_cntpct_get
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* @msg: Read the register that holds the 64-bit physical count value.
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* @return {__STATIC_INLINEu64} CompareValue, bits [63:0] Physical count value.
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*/
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__attribute__((always_inline)) __STATIC_INLINE u64 arm_aarch32_cntpct_get(void)
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{
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/* "r0" --- low,
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"r1" --- hi
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*/
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u32 low;
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u32 hi;
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__asm__ volatile(
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".word 0xec510f0e \n" /* mrrc p15, 0, r0, r1, c14 */
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"mov %0, r0 \n"
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"mov %1, r1 \n"
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: "=&r"(low), "=&r"(hi));
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return (((u64)hi) << 32) | low;
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}
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#define IRQ_DISABLE() \
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__asm volatile("CPSID i" :: \
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: "memory"); \
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__asm volatile("DSB"); \
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__asm volatile("ISB");
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#define IRQ_ENABLE() \
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__asm volatile("CPSIE i" :: \
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: "memory"); \
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__asm volatile("DSB"); \
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__asm volatile("ISB");
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/* the exception stack without VFP registers */
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struct ft_hw_exp_stack
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{
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u32 r0;
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u32 r1;
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u32 r2;
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u32 r3;
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u32 r4;
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u32 r5;
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u32 r6;
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u32 r7;
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u32 r8;
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u32 r9;
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u32 r10;
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u32 fp;
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u32 ip;
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u32 sp;
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u32 lr;
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u32 pc;
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u32 cpsr;
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};
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#ifdef __cplusplus
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}
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#endif
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#endif // !
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