rt-thread-official/bsp/Vango/v85xx/drivers/drv_spi.c

208 lines
5.4 KiB
C
Raw Normal View History

2021-09-21 14:56:40 +08:00
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
2021-09-21 14:56:40 +08:00
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-06-05 tanek first implementation.
* 2018-04-19 misonyo Porting for v85xxf30x
* 2019-03-31 xuzhuoyi Porting for v85xxe230
* 2021-09-21 zhuxw Porting for v85xx
2021-09-21 14:56:40 +08:00
*/
#include "drv_spi.h"
#include "board.h"
#include <rtthread.h>
#if defined(RT_USING_SPI) && defined(RT_USING_PIN)
#include <rtdevice.h>
#if !defined(RT_USING_SPI1) && !defined(RT_USING_SPI2)
2021-09-21 14:56:40 +08:00
#error "Please define at least one SPIx"
#endif
/* private rt-thread spi ops function */
static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configuration* configuration);
static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* message);
static struct rt_spi_ops v85xx_spi_ops =
2021-09-21 14:56:40 +08:00
{
configure,
xfer
};
static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configuration* configuration)
{
SPI_InitType spi_init_struct;
2021-09-21 14:56:40 +08:00
rt_uint32_t spi_periph = (rt_uint32_t)device->bus->parent.user_data;
RT_ASSERT(device != RT_NULL);
RT_ASSERT(configuration != RT_NULL);
if(configuration->data_width > 8)
2021-09-21 14:56:40 +08:00
{
return RT_EIO;
}
{
rt_uint32_t spi_apb_clock;
rt_uint32_t max_hz;
max_hz = configuration->max_hz;
spi_apb_clock = CLK_GetPCLKFreq();
2021-09-21 14:56:40 +08:00
if(max_hz >= spi_apb_clock/2)
{
spi_init_struct.ClockDivision = SPI_CLKDIV_2;
2021-09-21 14:56:40 +08:00
}
else if (max_hz >= spi_apb_clock/4)
{
spi_init_struct.ClockDivision = SPI_CLKDIV_4;
2021-09-21 14:56:40 +08:00
}
else if (max_hz >= spi_apb_clock/8)
{
spi_init_struct.ClockDivision = SPI_CLKDIV_8;
2021-09-21 14:56:40 +08:00
}
else if (max_hz >= spi_apb_clock/16)
{
spi_init_struct.ClockDivision = SPI_CLKDIV_16;
2021-09-21 14:56:40 +08:00
}
else if (max_hz >= spi_apb_clock/32)
{
spi_init_struct.ClockDivision = SPI_CLKDIV_32;
2021-09-21 14:56:40 +08:00
}
else if (max_hz >= spi_apb_clock/64)
{
spi_init_struct.ClockDivision = SPI_CLKDIV_64;
2021-09-21 14:56:40 +08:00
}
else
{
/* min prescaler 128 */
spi_init_struct.ClockDivision = SPI_CLKDIV_128;
2021-09-21 14:56:40 +08:00
}
} /* baudrate */
switch(configuration->mode & RT_SPI_MODE_3)
{
case RT_SPI_MODE_0:
spi_init_struct.SPH = SPI_SPH_0;
spi_init_struct.SPO = SPI_SPO_0;
2021-09-21 14:56:40 +08:00
break;
case RT_SPI_MODE_1:
spi_init_struct.SPH = SPI_SPH_1;
spi_init_struct.SPO = SPI_SPO_0;
2021-09-21 14:56:40 +08:00
break;
case RT_SPI_MODE_2:
spi_init_struct.SPH = SPI_SPH_0;
spi_init_struct.SPO = SPI_SPO_1;
2021-09-21 14:56:40 +08:00
break;
case RT_SPI_MODE_3:
spi_init_struct.SPH = SPI_SPH_1;
spi_init_struct.SPO = SPI_SPO_1;
2021-09-21 14:56:40 +08:00
break;
}
if(!(configuration->mode & RT_SPI_MSB))
2021-09-21 14:56:40 +08:00
{
return RT_EIO;
2021-09-21 14:56:40 +08:00
}
spi_init_struct.Mode = SPI_MODE_MASTER;
spi_init_struct.CSNSoft = SPI_CSNSOFT_ENABLE;
2021-09-21 14:56:40 +08:00
SPI_Init((SPI_TypeDef*)spi_periph, &spi_init_struct);
2021-09-21 14:56:40 +08:00
SPI_Cmd((SPI_TypeDef*)spi_periph, ENABLE);
2021-09-21 14:56:40 +08:00
return RT_EOK;
};
static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* message)
{
rt_base_t v85xx_cs_pin = (rt_base_t)device->parent.user_data;
2021-09-21 14:56:40 +08:00
rt_uint32_t spi_periph = (rt_uint32_t)device->bus->parent.user_data;
struct rt_spi_configuration * config = &device->config;
2021-09-26 14:13:38 +08:00
RT_ASSERT(device != RT_NULL);
RT_ASSERT(message != RT_NULL);
2021-09-21 14:56:40 +08:00
/* take CS */
if(message->cs_take)
{
rt_pin_write(v85xx_cs_pin, PIN_LOW);
2021-09-21 14:56:40 +08:00
DEBUG_PRINTF("spi take cs\n");
}
{
if(config->data_width <= 8)
{
const rt_uint8_t * send_ptr = message->send_buf;
rt_uint8_t * recv_ptr = message->recv_buf;
rt_uint32_t size = message->length;
DEBUG_PRINTF("spi poll transfer start: %d\n", size);
while(size--)
{
rt_uint8_t data = 0xFF;
if(send_ptr != RT_NULL)
{
data = *send_ptr++;
}
//Wait until the transmit buffer is empty
while(RESET == SPI_GetStatus((SPI_TypeDef*)spi_periph, SPI_STS_TXEMPTY));
2021-09-21 14:56:40 +08:00
// Send the byte
SPI_SendData((SPI_TypeDef*)spi_periph, data);
2021-09-21 14:56:40 +08:00
//Wait until a data is received
while(RESET == SPI_GetStatus((SPI_TypeDef*)spi_periph, SPI_STS_RNE));
2021-09-21 14:56:40 +08:00
// Get the received data
data = SPI_ReceiveData((SPI_TypeDef*)spi_periph);
2021-09-21 14:56:40 +08:00
if(recv_ptr != RT_NULL)
{
*recv_ptr++ = data;
}
}
DEBUG_PRINTF("spi poll transfer finsh\n");
}
}
/* release CS */
if(message->cs_release)
{
rt_pin_write(v85xx_cs_pin, PIN_HIGH);
2021-09-21 14:56:40 +08:00
DEBUG_PRINTF("spi release cs\n");
}
return message->length;
};
int v85xx_hw_spi_init(void)
2021-09-21 14:56:40 +08:00
{
int result = 0;
#ifdef RT_USING_SPI1
2021-09-21 14:56:40 +08:00
static struct rt_spi_bus spi_bus0;
spi_bus0.parent.user_data = (void *)SPI1;
2021-09-21 14:56:40 +08:00
result = rt_spi_bus_register(&spi_bus0, "spi1", &v85xx_spi_ops);
2021-09-21 14:56:40 +08:00
#endif
2021-09-21 14:56:40 +08:00
#ifdef RT_USING_SPI2
2021-09-21 14:56:40 +08:00
static struct rt_spi_bus spi_bus1;
spi_bus1.parent.user_data = (void *)SPI2;
2021-09-21 14:56:40 +08:00
result = rt_spi_bus_register(&spi_bus1, "spi2", &v85xx_spi_ops);
2021-09-21 14:56:40 +08:00
#endif
return result;
}
INIT_BOARD_EXPORT(v85xx_hw_spi_init);
2021-09-21 14:56:40 +08:00
#endif