113 lines
4.1 KiB
Plaintext
113 lines
4.1 KiB
Plaintext
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#! armcc -E
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/*
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** ###################################################################
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** Processors: MIMXRT1052CVL5A
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** MIMXRT1052DVL6A
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**
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** Compiler: Keil ARM C/C++ Compiler
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** Reference manual: IMXRT1050RM Rev.C, 08/2017
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** Version: rev. 0.1, 2017-01-10
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** Build: b170927
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**
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** Abstract:
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** Linker file for the Keil ARM C/C++ Compiler
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**
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** Copyright 2016 Freescale Semiconductor, Inc.
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** Copyright 2016-2017 NXP
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** Redistribution and use in source and binary forms, with or without modification,
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** are permitted provided that the following conditions are met:
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**
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** 1. Redistributions of source code must retain the above copyright notice, this list
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** of conditions and the following disclaimer.
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**
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** 2. Redistributions in binary form must reproduce the above copyright notice, this
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** list of conditions and the following disclaimer in the documentation and/or
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** other materials provided with the distribution.
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**
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** 3. Neither the name of the copyright holder nor the names of its
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** contributors may be used to endorse or promote products derived from this
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** software without specific prior written permission.
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**
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** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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**
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** http: www.nxp.com
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** mail: support@nxp.com
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**
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** ###################################################################
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*/
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#define m_flash_config_start 0x60000000
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#define m_flash_config_size 0x00001000
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#define m_ivt_start 0x60001000
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#define m_ivt_size 0x00001000
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#define m_text_start 0x60002000
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#define m_text_size 0x1F7FE000
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#define m_data_start 0x20000000
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#define m_data_size 0x00020000
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#define m_ncache_start 0x81E00000
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#define m_ncache_size 0x00200000
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/* Sizes */
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#if (defined(__stack_size__))
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#define Stack_Size __stack_size__
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#else
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#define Stack_Size 0x1000
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#endif
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#if (defined(__heap_size__))
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#define Heap_Size __heap_size__
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#else
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#define Heap_Size 0x0400
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#endif
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#define RTT_HEAP_SIZE (m_data_size-ImageLength(RW_m_data)-ImageLength(ARM_LIB_HEAP)-ImageLength(ARM_LIB_STACK))
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; load region size_region
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LR_IROM1 m_text_start m_text_size
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{
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ER_IROM1 m_text_start m_text_size ; load address = execution address
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{
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* (RESET,+FIRST)
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* (InRoot$$Sections)
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.ANY (+RO)
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}
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RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size ; RW data
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{
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.ANY (+RW +ZI)
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}
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ARM_LIB_HEAP +0 EMPTY Heap_Size{} ; Heap region growing up
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ARM_LIB_STACK +0 EMPTY Stack_Size{} ; Stack region growing down
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RTT_HEAP +0 EMPTY RTT_HEAP_SIZE{}
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; ncache RW data
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RW_m_ncache m_ncache_start m_ncache_size
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{
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* (NonCacheable.init)
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* (NonCacheable)
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}
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ITCM 0x400 0xFBFF {
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;drv_flexspi_hyper.o(+RO)
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;fsl_flexspi.o(+RO)
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* (*CLOCK_DisableClock)
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* (*CLOCK_ControlGate)
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* (*CLOCK_EnableClock)
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* (*CLOCK_SetDiv)
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* (itcm)
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}
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}
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