2021-10-18 14:50:00 +08:00
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/*
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2024-04-11 08:47:53 +08:00
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* Copyright (c) 2006-2024, RT-Thread Development Team
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2021-10-18 14:50:00 +08:00
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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2022-03-11 09:17:46 +08:00
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* Date Author Notes
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* 2021-07-29 KyleChan first version
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* 2022-01-19 Sherman add PIN2IRQX_TABLE
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2021-10-18 14:50:00 +08:00
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*/
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#include <drv_gpio.h>
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#ifdef RT_USING_PIN
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#define DBG_TAG "drv.gpio"
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#ifdef DRV_DEBUG
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2021-10-22 15:12:56 +08:00
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#define DBG_LVL DBG_LOG
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2021-10-18 14:50:00 +08:00
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#else
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2021-10-22 15:12:56 +08:00
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#define DBG_LVL DBG_INFO
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2021-10-18 14:50:00 +08:00
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#endif /* DRV_DEBUG */
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#ifdef R_ICU_H
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2022-03-11 09:17:46 +08:00
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#include "gpio_cfg.h"
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2021-10-18 14:50:00 +08:00
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static rt_base_t ra_pin_get_irqx(rt_uint32_t pin)
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{
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2022-03-11 09:17:46 +08:00
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PIN2IRQX_TABLE(pin)
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}
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2021-10-22 15:12:56 +08:00
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2022-03-11 09:17:46 +08:00
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static struct rt_pin_irq_hdr pin_irq_hdr_tab[RA_IRQ_MAX] = {0};
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struct ra_pin_irq_map pin_irq_map[RA_IRQ_MAX] = {0};
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2021-10-22 15:12:56 +08:00
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2022-03-11 09:17:46 +08:00
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static void ra_irq_tab_init(void)
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{
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for (int i = 0; i < RA_IRQ_MAX; ++i)
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{
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pin_irq_hdr_tab[i].pin = -1;
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pin_irq_hdr_tab[i].mode = 0;
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pin_irq_hdr_tab[i].args = RT_NULL;
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pin_irq_hdr_tab[i].hdr = RT_NULL;
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2021-10-18 14:50:00 +08:00
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}
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}
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static void ra_pin_map_init(void)
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{
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#ifdef VECTOR_NUMBER_ICU_IRQ0
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pin_irq_map[0].irq_ctrl = &g_external_irq0_ctrl;
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pin_irq_map[0].irq_cfg = &g_external_irq0_cfg;
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#endif
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#ifdef VECTOR_NUMBER_ICU_IRQ1
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pin_irq_map[1].irq_ctrl = &g_external_irq1_ctrl;
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pin_irq_map[1].irq_cfg = &g_external_irq1_cfg;
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#endif
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#ifdef VECTOR_NUMBER_ICU_IRQ2
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pin_irq_map[2].irq_ctrl = &g_external_irq2_ctrl;
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pin_irq_map[2].irq_cfg = &g_external_irq2_cfg;
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#endif
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#ifdef VECTOR_NUMBER_ICU_IRQ3
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pin_irq_map[3].irq_ctrl = &g_external_irq3_ctrl;
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pin_irq_map[3].irq_cfg = &g_external_irq3_cfg;
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#endif
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#ifdef VECTOR_NUMBER_ICU_IRQ4
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pin_irq_map[4].irq_ctrl = &g_external_irq4_ctrl;
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pin_irq_map[4].irq_cfg = &g_external_irq4_cfg;
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#endif
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#ifdef VECTOR_NUMBER_ICU_IRQ5
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pin_irq_map[5].irq_ctrl = &g_external_irq5_ctrl;
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pin_irq_map[5].irq_cfg = &g_external_irq5_cfg;
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#endif
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#ifdef VECTOR_NUMBER_ICU_IRQ6
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pin_irq_map[6].irq_ctrl = &g_external_irq6_ctrl;
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pin_irq_map[6].irq_cfg = &g_external_irq6_cfg;
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#endif
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#ifdef VECTOR_NUMBER_ICU_IRQ7
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pin_irq_map[7].irq_ctrl = &g_external_irq7_ctrl;
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pin_irq_map[7].irq_cfg = &g_external_irq7_cfg;
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#endif
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#ifdef VECTOR_NUMBER_ICU_IRQ8
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pin_irq_map[8].irq_ctrl = &g_external_irq8_ctrl;
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pin_irq_map[8].irq_cfg = &g_external_irq8_cfg;
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#endif
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#ifdef VECTOR_NUMBER_ICU_IRQ9
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pin_irq_map[9].irq_ctrl = &g_external_irq9_ctrl;
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pin_irq_map[9].irq_cfg = &g_external_irq9_cfg;
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#endif
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#ifdef VECTOR_NUMBER_ICU_IRQ10
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pin_irq_map[10].irq_ctrl = &g_external_irq10_ctrl;
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pin_irq_map[10].irq_cfg = &g_external_irq10_cfg;
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#endif
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#ifdef VECTOR_NUMBER_ICU_IRQ11
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pin_irq_map[11].irq_ctrl = &g_external_irq11_ctrl;
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pin_irq_map[11].irq_cfg = &g_external_irq11_cfg;
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#endif
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#ifdef VECTOR_NUMBER_ICU_IRQ12
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pin_irq_map[12].irq_ctrl = &g_external_irq12_ctrl;
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pin_irq_map[12].irq_cfg = &g_external_irq12_cfg;
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#endif
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#ifdef VECTOR_NUMBER_ICU_IRQ13
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pin_irq_map[13].irq_ctrl = &g_external_irq13_ctrl;
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pin_irq_map[13].irq_cfg = &g_external_irq13_cfg;
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#endif
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#ifdef VECTOR_NUMBER_ICU_IRQ14
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pin_irq_map[14].irq_ctrl = &g_external_irq14_ctrl;
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pin_irq_map[14].irq_cfg = &g_external_irq14_cfg;
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#endif
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#ifdef VECTOR_NUMBER_ICU_IRQ15
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pin_irq_map[15].irq_ctrl = &g_external_irq15_ctrl;
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pin_irq_map[15].irq_cfg = &g_external_irq15_cfg;
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#endif
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}
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#endif /* R_ICU_H */
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2023-04-19 00:32:42 +08:00
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static void ra_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
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2021-10-18 14:50:00 +08:00
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{
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fsp_err_t err;
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2024-04-15 17:13:10 +08:00
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/* Initialize the IOPORT module and configure the pins */
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err = R_IOPORT_Open(&g_ioport_ctrl, &g_bsp_pin_cfg);
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if (err != FSP_SUCCESS)
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{
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LOG_E("GPIO open failed");
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return;
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}
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2021-10-22 15:12:56 +08:00
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switch (mode)
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2021-10-18 14:50:00 +08:00
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{
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2021-10-22 15:12:56 +08:00
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case PIN_MODE_OUTPUT:
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2024-04-11 08:47:53 +08:00
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err = R_IOPORT_PinCfg(&g_ioport_ctrl, (bsp_io_port_pin_t)pin, BSP_IO_DIRECTION_OUTPUT);
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2021-10-22 15:12:56 +08:00
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if (err != FSP_SUCCESS)
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{
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LOG_E("PIN_MODE_OUTPUT configuration failed");
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return;
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}
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break;
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2021-10-18 14:50:00 +08:00
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2021-10-22 15:12:56 +08:00
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case PIN_MODE_INPUT:
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2024-04-11 08:47:53 +08:00
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err = R_IOPORT_PinCfg(&g_ioport_ctrl, (bsp_io_port_pin_t)pin, BSP_IO_DIRECTION_INPUT);
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2021-10-22 15:12:56 +08:00
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if (err != FSP_SUCCESS)
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{
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LOG_E("PIN_MODE_INPUT configuration failed");
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return;
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}
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break;
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2021-10-18 14:50:00 +08:00
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2021-10-22 15:12:56 +08:00
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case PIN_MODE_OUTPUT_OD:
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2024-04-11 08:47:53 +08:00
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err = R_IOPORT_PinCfg(&g_ioport_ctrl, (bsp_io_port_pin_t)pin, IOPORT_CFG_NMOS_ENABLE);
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2021-10-22 15:12:56 +08:00
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if (err != FSP_SUCCESS)
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{
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LOG_E("PIN_MODE_OUTPUT_OD configuration failed");
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return;
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}
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break;
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2021-10-18 14:50:00 +08:00
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}
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}
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2023-04-19 00:32:42 +08:00
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static void ra_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
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2021-10-18 14:50:00 +08:00
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{
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bsp_io_level_t level = BSP_IO_LEVEL_HIGH;
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if (value != level)
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{
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level = BSP_IO_LEVEL_LOW;
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}
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R_BSP_PinAccessEnable();
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2024-04-11 08:47:53 +08:00
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#ifdef SOC_SERIES_R9A07G0
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R_IOPORT_PinWrite(&g_ioport_ctrl, (bsp_io_port_pin_t)pin, (bsp_io_level_t)level);
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#else
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2021-10-18 14:50:00 +08:00
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R_BSP_PinWrite(pin, level);
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2024-04-11 08:47:53 +08:00
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#endif
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2021-10-18 14:50:00 +08:00
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R_BSP_PinAccessDisable();
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}
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2024-03-24 02:50:31 +08:00
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static rt_ssize_t ra_pin_read(rt_device_t dev, rt_base_t pin)
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2021-10-18 14:50:00 +08:00
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{
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if ((pin > RA_MAX_PIN_VALUE) || (pin < RA_MIN_PIN_VALUE))
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{
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2024-03-24 09:04:19 +08:00
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return -RT_EINVAL;
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2021-10-18 14:50:00 +08:00
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}
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2024-04-11 08:47:53 +08:00
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#ifdef SOC_SERIES_R9A07G0
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bsp_io_level_t io_level;
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R_IOPORT_PinRead(&g_ioport_ctrl, (bsp_io_port_pin_t)pin, &io_level);
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return io_level;
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#else
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2021-10-18 14:50:00 +08:00
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return R_BSP_PinRead(pin);
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2024-04-11 08:47:53 +08:00
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#endif
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2021-10-18 14:50:00 +08:00
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}
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2023-04-19 00:32:42 +08:00
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static rt_err_t ra_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled)
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2021-10-18 14:50:00 +08:00
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{
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#ifdef R_ICU_H
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rt_err_t err;
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rt_int32_t irqx = ra_pin_get_irqx(pin);
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2021-10-22 15:12:56 +08:00
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if (PIN_IRQ_ENABLE == enabled)
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2021-10-18 14:50:00 +08:00
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{
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2021-10-22 15:12:56 +08:00
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if (0 <= irqx && irqx < sizeof(pin_irq_map) / sizeof(pin_irq_map[0]))
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2021-10-18 14:50:00 +08:00
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{
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2021-10-22 15:12:56 +08:00
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err = R_ICU_ExternalIrqOpen((external_irq_ctrl_t *const)pin_irq_map[irqx].irq_ctrl,
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(external_irq_cfg_t const * const)pin_irq_map[irqx].irq_cfg);
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2021-10-18 14:50:00 +08:00
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/* Handle error */
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if (FSP_SUCCESS != err)
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{
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/* ICU Open failure message */
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LOG_E("\r\n**R_ICU_ExternalIrqOpen API FAILED**\r\n");
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return -RT_ERROR;
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}
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2021-10-22 15:12:56 +08:00
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err = R_ICU_ExternalIrqEnable((external_irq_ctrl_t *const)pin_irq_map[irqx].irq_ctrl);
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2021-10-18 14:50:00 +08:00
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/* Handle error */
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if (FSP_SUCCESS != err)
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{
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/* ICU Enable failure message */
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LOG_E("\r\n**R_ICU_ExternalIrqEnable API FAILED**\r\n");
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return -RT_ERROR;
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}
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}
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}
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2021-10-22 15:12:56 +08:00
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else if (PIN_IRQ_DISABLE == enabled)
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2021-10-18 14:50:00 +08:00
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{
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2021-10-22 15:12:56 +08:00
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err = R_ICU_ExternalIrqDisable((external_irq_ctrl_t *const)pin_irq_map[irqx].irq_ctrl);
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2021-10-18 14:50:00 +08:00
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if (FSP_SUCCESS != err)
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{
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/* ICU Disable failure message */
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LOG_E("\r\n**R_ICU_ExternalIrqDisable API FAILED**\r\n");
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return -RT_ERROR;
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}
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2021-10-22 15:12:56 +08:00
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err = R_ICU_ExternalIrqClose((external_irq_ctrl_t *const)pin_irq_map[irqx].irq_ctrl);
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2021-10-18 14:50:00 +08:00
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if (FSP_SUCCESS != err)
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{
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/* ICU Close failure message */
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LOG_E("\r\n**R_ICU_ExternalIrqClose API FAILED**\r\n");
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return -RT_ERROR;
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}
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}
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return RT_EOK;
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#else
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return -RT_ERROR;
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#endif
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}
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2023-04-19 00:32:42 +08:00
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static rt_err_t ra_pin_attach_irq(struct rt_device *device, rt_base_t pin,
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rt_uint8_t mode, void (*hdr)(void *args), void *args)
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2021-10-18 14:50:00 +08:00
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{
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#ifdef R_ICU_H
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rt_int32_t irqx = ra_pin_get_irqx(pin);
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2021-10-22 15:12:56 +08:00
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if (0 <= irqx && irqx < (sizeof(pin_irq_map) / sizeof(pin_irq_map[0])))
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2021-10-18 14:50:00 +08:00
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{
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2021-10-22 15:12:56 +08:00
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int level = rt_hw_interrupt_disable();
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if (pin_irq_hdr_tab[irqx].pin == irqx &&
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pin_irq_hdr_tab[irqx].hdr == hdr &&
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pin_irq_hdr_tab[irqx].mode == mode &&
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pin_irq_hdr_tab[irqx].args == args)
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{
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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if (pin_irq_hdr_tab[irqx].pin != -1)
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{
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rt_hw_interrupt_enable(level);
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2023-03-22 03:41:55 +08:00
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return -RT_EBUSY;
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2021-10-22 15:12:56 +08:00
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}
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pin_irq_hdr_tab[irqx].pin = irqx;
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pin_irq_hdr_tab[irqx].hdr = hdr;
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pin_irq_hdr_tab[irqx].mode = mode;
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pin_irq_hdr_tab[irqx].args = args;
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2021-10-18 14:50:00 +08:00
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rt_hw_interrupt_enable(level);
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}
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else return -RT_ERROR;
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return RT_EOK;
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#else
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return -RT_ERROR;
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#endif
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}
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2023-04-19 00:32:42 +08:00
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static rt_err_t ra_pin_dettach_irq(struct rt_device *device, rt_base_t pin)
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2021-10-18 14:50:00 +08:00
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{
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#ifdef R_ICU_H
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rt_int32_t irqx = ra_pin_get_irqx(pin);
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2021-10-22 15:12:56 +08:00
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if (0 <= irqx && irqx < sizeof(pin_irq_map) / sizeof(pin_irq_map[0]))
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2021-10-18 14:50:00 +08:00
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{
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int level = rt_hw_interrupt_disable();
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if (pin_irq_hdr_tab[irqx].pin == -1)
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{
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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|
|
pin_irq_hdr_tab[irqx].pin = -1;
|
|
|
|
pin_irq_hdr_tab[irqx].hdr = RT_NULL;
|
|
|
|
pin_irq_hdr_tab[irqx].mode = 0;
|
|
|
|
pin_irq_hdr_tab[irqx].args = RT_NULL;
|
|
|
|
rt_hw_interrupt_enable(level);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
return -RT_ERROR;
|
|
|
|
}
|
|
|
|
return RT_EOK;
|
|
|
|
#else
|
|
|
|
return -RT_ERROR;
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
static rt_base_t ra_pin_get(const char *name)
|
|
|
|
{
|
|
|
|
int pin_number = -1, port = -1, pin = -1;
|
2024-04-11 17:57:25 +08:00
|
|
|
|
2021-10-22 15:12:56 +08:00
|
|
|
if (rt_strlen(name) != 4)
|
2021-10-18 14:50:00 +08:00
|
|
|
return -1;
|
2024-04-11 17:57:25 +08:00
|
|
|
|
|
|
|
if ((name[0] == 'P' || name[0] == 'p'))
|
2021-10-18 14:50:00 +08:00
|
|
|
{
|
2024-04-11 17:57:25 +08:00
|
|
|
if ('0' <= name[1] && name[1] <= '9')
|
|
|
|
{
|
|
|
|
port = (name[1] - '0') * 16 * 16;
|
|
|
|
if ('0' <= name[2] && name[2] <= '9' && '0' <= name[3] && name[3] <= '9')
|
|
|
|
{
|
|
|
|
pin = (name[2] - '0') * 10 + (name[3] - '0');
|
|
|
|
pin_number = port + pin;
|
|
|
|
|
|
|
|
return pin_number;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else if ('A' <= name[1] && name[1] <= 'Z')
|
2021-10-18 14:50:00 +08:00
|
|
|
{
|
2024-04-11 17:57:25 +08:00
|
|
|
port = (name[1] - '0' - 7) * 16 * 16;
|
|
|
|
if ('0' <= name[2] && name[2] <= '9' && '0' <= name[3] && name[3] <= '9')
|
2021-10-18 14:50:00 +08:00
|
|
|
{
|
2024-04-11 17:57:25 +08:00
|
|
|
pin = (name[2] - '0') * 10 + (name[3] - '0');
|
|
|
|
pin_number = port + pin;
|
|
|
|
|
|
|
|
return pin_number;
|
2021-10-18 14:50:00 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2024-04-11 17:57:25 +08:00
|
|
|
return -1;
|
2021-10-18 14:50:00 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
const static struct rt_pin_ops _ra_pin_ops =
|
|
|
|
{
|
|
|
|
.pin_mode = ra_pin_mode,
|
|
|
|
.pin_write = ra_pin_write,
|
|
|
|
.pin_read = ra_pin_read,
|
|
|
|
.pin_attach_irq = ra_pin_attach_irq,
|
|
|
|
.pin_detach_irq = ra_pin_dettach_irq,
|
|
|
|
.pin_irq_enable = ra_pin_irq_enable,
|
|
|
|
.pin_get = ra_pin_get,
|
|
|
|
};
|
|
|
|
|
|
|
|
int rt_hw_pin_init(void)
|
|
|
|
{
|
|
|
|
#ifdef R_ICU_H
|
2022-03-11 09:17:46 +08:00
|
|
|
ra_irq_tab_init();
|
2021-10-18 14:50:00 +08:00
|
|
|
ra_pin_map_init();
|
|
|
|
#endif
|
2024-04-01 08:31:27 +08:00
|
|
|
|
2021-10-18 14:50:00 +08:00
|
|
|
return rt_device_pin_register("pin", &_ra_pin_ops, RT_NULL);
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef R_ICU_H
|
2022-07-07 17:12:56 +08:00
|
|
|
void irq_callback(external_irq_callback_args_t *p_args)
|
2021-10-18 14:50:00 +08:00
|
|
|
{
|
|
|
|
rt_interrupt_enter();
|
2022-07-07 17:12:56 +08:00
|
|
|
if (p_args->channel == pin_irq_hdr_tab[p_args->channel].pin)
|
2021-10-18 14:50:00 +08:00
|
|
|
{
|
2022-07-07 17:12:56 +08:00
|
|
|
pin_irq_hdr_tab[p_args->channel].hdr(pin_irq_hdr_tab[p_args->channel].args);
|
2021-10-18 14:50:00 +08:00
|
|
|
}
|
|
|
|
rt_interrupt_leave();
|
|
|
|
};
|
|
|
|
#endif /* R_ICU_H */
|
|
|
|
|
|
|
|
#endif /* RT_USING_PIN */
|