247 lines
8.9 KiB
C
247 lines
8.9 KiB
C
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/*
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** ###################################################################
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** Processors: MIMXRT1021CAF4A
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** MIMXRT1021CAG4A
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** MIMXRT1021DAF5A
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** MIMXRT1021DAG5A
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**
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** Compilers: Keil ARM C/C++ Compiler
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** Freescale C/C++ for Embedded ARM
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** GNU C Compiler
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** IAR ANSI C/C++ Compiler for ARM
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** MCUXpresso Compiler
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**
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** Reference manual: IMXRT1020RM Rev. C, 02/2018
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** Version: rev. 0.1, 2017-11-06
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** Build: b180316
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**
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** Abstract:
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** Provides a system configuration function and a global variable that
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** contains the system frequency. It configures the device and initializes
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** the oscillator (PLL) that is part of the microcontroller device.
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**
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** The Clear BSD License
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** Copyright 2016 Freescale Semiconductor, Inc.
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** Copyright 2016-2018 NXP
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** All rights reserved.
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**
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** Redistribution and use in source and binary forms, with or without
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** modification, are permitted (subject to the limitations in the
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** disclaimer below) provided that the following conditions are met:
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**
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** * Redistributions of source code must retain the above copyright
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** notice, this list of conditions and the following disclaimer.
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**
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** * Redistributions in binary form must reproduce the above copyright
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** notice, this list of conditions and the following disclaimer in the
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** documentation and/or other materials provided with the distribution.
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**
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** * Neither the name of the copyright holder nor the names of its
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** contributors may be used to endorse or promote products derived from
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** this software without specific prior written permission.
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**
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** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
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** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
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** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
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** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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**
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** http: www.nxp.com
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** mail: support@nxp.com
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**
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** Revisions:
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** - rev. 0.1 (2017-11-06)
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** Initial version.
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**
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** ###################################################################
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*/
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/*!
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* @file MIMXRT1021
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* @version 0.1
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* @date 2017-11-06
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* @brief Device specific configuration file for MIMXRT1021 (implementation file)
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*
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* Provides a system configuration function and a global variable that contains
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* the system frequency. It configures the device and initializes the oscillator
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* (PLL) that is part of the microcontroller device.
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*/
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#include <stdint.h>
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#include "fsl_device_registers.h"
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/* ----------------------------------------------------------------------------
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-- Core clock
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---------------------------------------------------------------------------- */
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uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
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/* ----------------------------------------------------------------------------
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-- SystemInit()
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---------------------------------------------------------------------------- */
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void SystemInit (void) {
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#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
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SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
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#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
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#if defined(__MCUXPRESSO)
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extern uint32_t g_pfnVectors[]; // Vector table defined in startup code
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SCB->VTOR = (uint32_t)g_pfnVectors;
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#endif
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/* Disable Watchdog Power Down Counter */
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WDOG1->WMCR &= ~WDOG_WMCR_PDE_MASK;
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WDOG2->WMCR &= ~WDOG_WMCR_PDE_MASK;
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/* Watchdog disable */
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#if (DISABLE_WDOG)
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if (WDOG1->WCR & WDOG_WCR_WDE_MASK)
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{
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WDOG1->WCR &= ~WDOG_WCR_WDE_MASK;
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}
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if (WDOG2->WCR & WDOG_WCR_WDE_MASK)
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{
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WDOG2->WCR &= ~WDOG_WCR_WDE_MASK;
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}
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RTWDOG->CNT = 0xD928C520U; /* 0xD928C520U is the update key */
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RTWDOG->TOVAL = 0xFFFF;
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RTWDOG->CS = (uint32_t) ((RTWDOG->CS) & ~RTWDOG_CS_EN_MASK) | RTWDOG_CS_UPDATE_MASK;
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#endif /* (DISABLE_WDOG) */
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/* Disable Systick which might be enabled by bootrom */
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if (SysTick->CTRL & SysTick_CTRL_ENABLE_Msk)
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{
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SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
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}
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/* Enable instruction and data caches */
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#if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT
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if (SCB_CCR_IC_Msk != (SCB_CCR_IC_Msk & SCB->CCR)) {
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SCB_EnableICache();
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}
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#endif
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#if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT
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if (SCB_CCR_DC_Msk != (SCB_CCR_DC_Msk & SCB->CCR)) {
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SCB_EnableDCache();
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}
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#endif
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/* Suggest to add it in assembly file */
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// IOMUXC_GPR->GPR17 = 0x0000AAA5;//
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// IOMUXC_GPR->GPR16 |= 0x00000007;
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SystemInitHook();
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}
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/* ----------------------------------------------------------------------------
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-- SystemCoreClockUpdate()
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---------------------------------------------------------------------------- */
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void SystemCoreClockUpdate (void) {
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uint32_t freq;
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uint32_t PLL2MainClock;
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uint32_t PLL3MainClock;
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/* Check if system pll is bypassed */
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if(CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_MASK)
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{
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PLL2MainClock = CPU_XTAL_CLK_HZ;
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}
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else
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{
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PLL2MainClock = (CPU_XTAL_CLK_HZ * ((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) ? 22U : 20U));
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}
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PLL2MainClock += ((uint64_t)CPU_XTAL_CLK_HZ * ((uint64_t)(CCM_ANALOG->PLL_SYS_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_SYS_DENOM));
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/* Check if usb1 pll is bypassed */
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if(CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_BYPASS_MASK)
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{
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PLL3MainClock = CPU_XTAL_CLK_HZ;
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}
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else
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{
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PLL3MainClock = (CPU_XTAL_CLK_HZ * ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) ? 22U : 20U));
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}
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/* Periph_clk2_clk ---> Periph_clk */
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if (CCM->CBCDR & CCM_CBCDR_PERIPH_CLK_SEL_MASK)
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{
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switch (CCM->CBCMR & CCM_CBCMR_PERIPH_CLK2_SEL_MASK)
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{
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/* Pll3_sw_clk ---> Periph_clk2_clk ---> Periph_clk ---> Core_clock */
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case CCM_CBCMR_PERIPH_CLK2_SEL(0U):
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freq = PLL3MainClock;
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break;
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/* Osc_clk ---> Periph_clk2_clk ---> Periph_clk ---> Core_clock */
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case CCM_CBCMR_PERIPH_CLK2_SEL(1U):
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freq = CPU_XTAL_CLK_HZ;
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break;
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/* Pll2_bypass_clk ---> Periph_clk2_clk ---> Periph_clk ---> Core_clock */
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case CCM_CBCMR_PERIPH_CLK2_SEL(2U):
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freq = CPU_XTAL_CLK_HZ;
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case CCM_CBCMR_PERIPH_CLK2_SEL(3U):
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default:
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freq = 0U;
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break;
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}
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freq /= (((CCM->CBCDR & CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >> CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) + 1U);
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}
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/* Pre_Periph_clk ---> Periph_clk */
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else
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{
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switch (CCM->CBCMR & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
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{
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/* PLL2 ---> Pre_Periph_clk ---> Periph_clk ---> Core_clock */
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case CCM_CBCMR_PRE_PERIPH_CLK_SEL(0U):
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freq = PLL2MainClock;
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break;
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/* PLL3 PFD3 ---> Pre_Periph_clk ---> Periph_clk ---> Core_clock */
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case CCM_CBCMR_PRE_PERIPH_CLK_SEL(1U):
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freq = PLL3MainClock / ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD3_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT) * 18U;
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break;
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/* PLL2 PFD3 ---> Pre_Periph_clk ---> Periph_clk ---> Core_clock */
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case CCM_CBCMR_PRE_PERIPH_CLK_SEL(2U):
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freq = PLL2MainClock / ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD3_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT) * 18U;
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break;
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/* PLL6 ---> Pre_Periph_clk ---> Periph_clk ---> Core_clock */
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case CCM_CBCMR_PRE_PERIPH_CLK_SEL(3U):
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freq = 500000000U / (((CCM->CACRR & CCM_CACRR_ARM_PODF_MASK) >> CCM_CACRR_ARM_PODF_SHIFT) + 1U);
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break;
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default:
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freq = 0U;
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break;
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}
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}
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SystemCoreClock = (freq / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U));
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}
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/* ----------------------------------------------------------------------------
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-- SystemInitHook()
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---------------------------------------------------------------------------- */
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__attribute__ ((weak)) void SystemInitHook (void) {
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/* Void implementation of the weak function. */
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}
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