352 lines
12 KiB
C
352 lines
12 KiB
C
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/*
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* The Clear BSD License
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* Copyright (c) 2017, NXP
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* All rights reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted (subject to the limitations in the disclaimer below) provided
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* that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "fsl_dcdc.h"
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.dcdc_1"
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#endif
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*!
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* @brief Get instance number for DCDC module.
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*
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* @param base DCDC peripheral base address
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*/
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static uint32_t DCDC_GetInstance(DCDC_Type *base);
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*! @brief Pointers to DCDC bases for each instance. */
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static DCDC_Type *const s_dcdcBases[] = DCDC_BASE_PTRS;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/*! @brief Pointers to DCDC clocks for each instance. */
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static const clock_ip_name_t s_dcdcClocks[] = DCDC_CLOCKS;
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/*******************************************************************************
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* Code
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******************************************************************************/
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static uint32_t DCDC_GetInstance(DCDC_Type *base)
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{
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uint32_t instance;
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/* Find the instance index from base address mappings. */
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for (instance = 0; instance < ARRAY_SIZE(s_dcdcBases); instance++)
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{
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if (s_dcdcBases[instance] == base)
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{
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break;
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}
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}
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assert(instance < ARRAY_SIZE(s_dcdcBases));
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return instance;
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}
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void DCDC_Init(DCDC_Type *base)
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{
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Enable the clock. */
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CLOCK_EnableClock(s_dcdcClocks[DCDC_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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}
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void DCDC_Deinit(DCDC_Type *base)
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{
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Disable the clock. */
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CLOCK_DisableClock(s_dcdcClocks[DCDC_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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}
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void DCDC_SetClockSource(DCDC_Type *base, dcdc_clock_source_t clockSource)
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{
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uint32_t tmp32;
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/* Configure the DCDC_REG0 register. */
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tmp32 = base->REG0 &
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~(DCDC_REG0_XTAL_24M_OK_MASK | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | DCDC_REG0_SEL_CLK_MASK |
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DCDC_REG0_PWD_OSC_INT_MASK);
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switch (clockSource)
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{
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case kDCDC_ClockInternalOsc:
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tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK;
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break;
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case kDCDC_ClockExternalOsc:
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/* Choose the external clock and disable the internal clock. */
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tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | DCDC_REG0_SEL_CLK_MASK | DCDC_REG0_PWD_OSC_INT_MASK;
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break;
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case kDCDC_ClockAutoSwitch:
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/* Set to switch from internal ring osc to xtal 24M if auto mode is enabled. */
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tmp32 |= DCDC_REG0_XTAL_24M_OK_MASK;
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break;
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default:
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break;
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}
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base->REG0 = tmp32;
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}
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void DCDC_GetDefaultDetectionConfig(dcdc_detection_config_t *config)
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{
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assert(NULL != config);
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config->enableXtalokDetection = false;
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config->powerDownOverVoltageDetection = true;
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config->powerDownLowVlotageDetection = false;
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config->powerDownOverCurrentDetection = true;
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config->powerDownPeakCurrentDetection = true;
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config->powerDownZeroCrossDetection = true;
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config->OverCurrentThreshold = kDCDC_OverCurrentThresholdAlt0;
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config->PeakCurrentThreshold = kDCDC_PeakCurrentThresholdAlt0;
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}
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void DCDC_SetDetectionConfig(DCDC_Type *base, const dcdc_detection_config_t *config)
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{
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assert(NULL != config);
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uint32_t tmp32;
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/* Configure the DCDC_REG0 register. */
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tmp32 = base->REG0 &
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~(DCDC_REG0_XTALOK_DISABLE_MASK | DCDC_REG0_PWD_HIGH_VOLT_DET_MASK | DCDC_REG0_PWD_CMP_BATT_DET_MASK |
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DCDC_REG0_PWD_OVERCUR_DET_MASK | DCDC_REG0_PWD_CUR_SNS_CMP_MASK | DCDC_REG0_PWD_ZCD_MASK |
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DCDC_REG0_CUR_SNS_THRSH_MASK | DCDC_REG0_OVERCUR_TRIG_ADJ_MASK);
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tmp32 |= DCDC_REG0_CUR_SNS_THRSH(config->PeakCurrentThreshold) |
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DCDC_REG0_OVERCUR_TRIG_ADJ(config->OverCurrentThreshold);
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if (false == config->enableXtalokDetection)
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{
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tmp32 |= DCDC_REG0_XTALOK_DISABLE_MASK;
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}
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if (config->powerDownOverVoltageDetection)
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{
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tmp32 |= DCDC_REG0_PWD_HIGH_VOLT_DET_MASK;
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}
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if (config->powerDownLowVlotageDetection)
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{
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tmp32 |= DCDC_REG0_PWD_CMP_BATT_DET_MASK;
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}
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if (config->powerDownOverCurrentDetection)
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{
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tmp32 |= DCDC_REG0_PWD_OVERCUR_DET_MASK;
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}
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if (config->powerDownPeakCurrentDetection)
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{
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tmp32 |= DCDC_REG0_PWD_CUR_SNS_CMP_MASK;
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}
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if (config->powerDownZeroCrossDetection)
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{
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tmp32 |= DCDC_REG0_PWD_ZCD_MASK;
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}
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base->REG0 = tmp32;
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}
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void DCDC_GetDefaultLowPowerConfig(dcdc_low_power_config_t *config)
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{
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assert(NULL != config);
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config->enableOverloadDetection = true;
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config->enableAdjustHystereticValue = false;
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config->countChargingTimePeriod = kDCDC_CountChargingTimePeriod8Cycle;
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config->countChargingTimeThreshold = kDCDC_CountChargingTimeThreshold32;
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}
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void DCDC_SetLowPowerConfig(DCDC_Type *base, const dcdc_low_power_config_t *config)
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{
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assert(NULL != config);
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uint32_t tmp32;
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/* Configure the DCDC_REG0 register. */
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tmp32 = base->REG0 &
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~(DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK | DCDC_REG0_LP_HIGH_HYS_MASK | DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK |
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DCDC_REG0_LP_OVERLOAD_THRSH_MASK);
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tmp32 |= DCDC_REG0_LP_OVERLOAD_FREQ_SEL(config->countChargingTimePeriod) |
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DCDC_REG0_LP_OVERLOAD_THRSH(config->countChargingTimeThreshold);
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if (config->enableOverloadDetection)
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{
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tmp32 |= DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK;
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}
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if (config->enableAdjustHystereticValue)
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{
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tmp32 |= DCDC_REG0_LP_HIGH_HYS_MASK;
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}
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base->REG0 = tmp32;
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}
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uint32_t DCDC_GetstatusFlags(DCDC_Type *base)
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{
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uint32_t tmp32 = 0U;
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if (DCDC_REG0_STS_DC_OK_MASK == (DCDC_REG0_STS_DC_OK_MASK & base->REG0))
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{
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tmp32 |= kDCDC_LockedOKStatus;
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}
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return tmp32;
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}
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void DCDC_ResetCurrentAlertSignal(DCDC_Type *base, bool enable)
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{
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if (enable)
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{
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base->REG0 |= DCDC_REG0_CURRENT_ALERT_RESET_MASK;
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}
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else
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{
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base->REG0 &= ~DCDC_REG0_CURRENT_ALERT_RESET_MASK;
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}
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}
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void DCDC_GetDefaultLoopControlConfig(dcdc_loop_control_config_t *config)
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{
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assert(NULL != config);
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config->enableCommonHysteresis = false;
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config->enableCommonThresholdDetection = false;
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config->enableInvertHysteresisSign = false;
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config->enableRCThresholdDetection = false;
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config->enableRCScaleCircuit = 0U;
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config->complementFeedForwardStep = 0U;
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config->controlParameterMagnitude = 2U;
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config->integralProportionalRatio = 2U;
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}
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void DCDC_SetLoopControlConfig(DCDC_Type *base, const dcdc_loop_control_config_t *config)
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{
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assert(NULL != config);
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uint32_t tmp32;
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/* Configure the DCDC_REG1 register. */
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tmp32 = base->REG1 & ~(DCDC_REG1_LOOPCTRL_EN_HYST_MASK | DCDC_REG1_LOOPCTRL_HST_THRESH_MASK);
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if (config->enableCommonHysteresis)
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{
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tmp32 |= DCDC_REG1_LOOPCTRL_EN_HYST_MASK;
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}
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if (config->enableCommonThresholdDetection)
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{
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tmp32 |= DCDC_REG1_LOOPCTRL_HST_THRESH_MASK;
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}
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base->REG1 = tmp32;
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/* configure the DCDC_REG2 register. */
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tmp32 = base->REG2 &
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~(DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK | DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK |
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DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK | DCDC_REG2_LOOPCTRL_DC_FF_MASK | DCDC_REG2_LOOPCTRL_DC_R_MASK |
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DCDC_REG2_LOOPCTRL_DC_C_MASK);
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tmp32 |= DCDC_REG2_LOOPCTRL_DC_FF(config->complementFeedForwardStep) |
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DCDC_REG2_LOOPCTRL_DC_R(config->controlParameterMagnitude) |
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DCDC_REG2_LOOPCTRL_DC_C(config->integralProportionalRatio) |
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DCDC_REG2_LOOPCTRL_EN_RCSCALE(config->enableRCScaleCircuit);
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if (config->enableInvertHysteresisSign)
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{
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tmp32 |= DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK;
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}
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if (config->enableRCThresholdDetection)
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{
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tmp32 |= DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK;
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}
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base->REG2 = tmp32;
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}
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void DCDC_SetMinPowerConfig(DCDC_Type *base, const dcdc_min_power_config_t *config)
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{
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assert(NULL != config);
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uint32_t tmp32;
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tmp32 = base->REG3 & ~DCDC_REG3_MINPWR_DC_HALFCLK_MASK;
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if (config->enableUseHalfFreqForContinuous)
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{
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tmp32 |= DCDC_REG3_MINPWR_DC_HALFCLK_MASK;
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}
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base->REG3 = tmp32;
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}
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void DCDC_AdjustTargetVoltage(DCDC_Type *base, uint32_t VDDRun, uint32_t VDDStandby)
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{
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uint32_t tmp32;
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/* Unlock the step for the output. */
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base->REG3 &= ~DCDC_REG3_DISABLE_STEP_MASK;
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/* Configure the DCDC_REG3 register. */
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tmp32 = base->REG3 & ~(DCDC_REG3_TARGET_LP_MASK | DCDC_REG3_TRG_MASK);
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tmp32 |= DCDC_REG3_TARGET_LP(VDDStandby) | DCDC_REG3_TRG(VDDRun);
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base->REG3 = tmp32;
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/* DCDC_STS_DC_OK bit will be de-asserted after target register changes. After output voltage settling to new
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* target value, DCDC_STS_DC_OK will be asserted. */
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while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0))
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{
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}
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}
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void DCDC_SetInternalRegulatorConfig(DCDC_Type *base, const dcdc_internal_regulator_config_t *config)
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{
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assert(NULL != config);
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uint32_t tmp32;
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/* Configure the DCDC_REG1 register. */
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tmp32 = base->REG1 & ~(DCDC_REG1_REG_FBK_SEL_MASK | DCDC_REG1_REG_RLOAD_SW_MASK);
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tmp32 |= DCDC_REG1_REG_FBK_SEL(config->feedbackPoint);
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if (config->enableLoadResistor)
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{
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tmp32 |= DCDC_REG1_REG_RLOAD_SW_MASK;
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}
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base->REG1 = tmp32;
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}
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void DCDC_BootIntoDCM(DCDC_Type *base)
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{
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base->REG0 &= ~(DCDC_REG0_PWD_ZCD_MASK | DCDC_REG0_PWD_CMP_OFFSET_MASK);
|
||
|
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base->REG2 = (~DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK & base->REG2) | DCDC_REG2_LOOPCTRL_EN_RCSCALE(0x4U) |
|
||
|
|
DCDC_REG2_DCM_SET_CTRL_MASK;
|
||
|
|
}
|
||
|
|
|
||
|
|
void DCDC_BootIntoCCM(DCDC_Type *base)
|
||
|
|
{
|
||
|
|
base->REG0 = (~DCDC_REG0_PWD_CMP_OFFSET_MASK & base->REG0) | DCDC_REG0_PWD_ZCD_MASK;
|
||
|
|
base->REG2 = (~DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK & base->REG2) | DCDC_REG2_LOOPCTRL_EN_RCSCALE(0x3U);
|
||
|
|
}
|