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58 lines
2.0 KiB
C
58 lines
2.0 KiB
C
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/*
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* Copyright (c) 2024 HPMicro
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef _HPM_PPI_H
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#define _HPM_PPI_H
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/*---------------------------------------------------------------------
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* Includes
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*---------------------------------------------------------------------
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*/
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#include "hpm_ppi_drv.h"
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/**
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* @brief ppi async sram config structure
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*
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*/
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typedef struct {
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uint32_t base_address; /**< external SRAM base address, should be 1MB aligned */
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uint32_t size_in_byte; /**< external SRAM size in byte */
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ppi_port_size_t port_size; /**< port size */
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bool ad_mux_mode; /**< addr and data mux mode */
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bool cs_valid_polarity; /**< cs valid polarity */
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bool dm_valid_polarity; /**< dm valid polarity */
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bool addr_valid_polarity; /**< addr valid polarity */
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uint8_t adv_ctrl_pin; /**< adv ctrl pin number, 0 - 7 */
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uint8_t rel_ctrl_pin; /**< rel ctrl pin number, 0 - 7 */
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uint8_t wel_ctrl_pin; /**< wel ctrl pin number, 0 - 7 */
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uint8_t as_in_ns; /**< address setup time */
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uint8_t ah_in_ns; /**< address hold time */
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uint8_t rel_in_ns; /**< RE low time */
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uint8_t reh_in_ns; /**< RE high time */
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uint8_t wel_in_ns; /**< WE low time */
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uint8_t weh_in_ns; /**< WE high time */
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} ppi_async_sram_config_t;
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#if defined(__cplusplus)
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extern "C" {
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#endif /* __cplusplus */
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/**
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* @brief config async sram
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*
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* @param[in] ppi PPI base address
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* @param[in] cs_index cs index, value: 0 - 3
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* @param[in] cmd_index cmd start index
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* @param[in] config async sram config structure pointer, @ref ppi_async_sram_config_t
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*/
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void ppi_config_async_sram(PPI_Type *ppi, uint8_t cs_index, uint8_t cmd_start_index, ppi_async_sram_config_t *config);
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#if defined(__cplusplus)
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}
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#endif /* __cplusplus */
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#endif /* _HPM_PPI_H */
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