2018-12-08 10:41:38 +08:00
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/*
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2023-01-05 10:06:09 +08:00
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* Copyright (c) 2006-2023, RT-Thread Development Team
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2018-12-08 10:41:38 +08:00
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018-10-03 Bernard The first version
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2020-11-20 12:05:37 +08:00
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* 2020/11/20 BalanceTWK Add FPU support
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2023-01-05 10:06:09 +08:00
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* 2023/01/04 WangShun Adapt to CH32
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2018-12-08 10:41:38 +08:00
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*/
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#ifndef CPUPORT_H__
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#define CPUPORT_H__
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#include <rtconfig.h>
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2023-01-05 10:06:09 +08:00
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#if !defined(__ASSEMBLY__)
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#if defined(SOC_RISCV_FAMILY_CH32)
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#include "interrupt.h"
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#endif
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#endif
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2018-12-08 10:41:38 +08:00
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2022-12-03 12:07:44 +08:00
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#ifndef __ASSEMBLY__
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#ifdef RT_USING_SMP
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typedef union {
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unsigned long slock;
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struct __arch_tickets {
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unsigned short owner;
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unsigned short next;
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} tickets;
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} rt_hw_spinlock_t;
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#endif
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#endif
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2018-12-08 10:41:38 +08:00
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/* bytes of register width */
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#ifdef ARCH_CPU_64BIT
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#define STORE sd
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#define LOAD ld
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#define REGBYTES 8
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#else
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#define STORE sw
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#define LOAD lw
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#define REGBYTES 4
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#endif
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2020-11-20 12:05:37 +08:00
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#ifdef ARCH_RISCV_FPU
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#ifdef ARCH_RISCV_FPU_D
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#define FSTORE fsd
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#define FLOAD fld
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#define FREGBYTES 8
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2021-03-27 17:51:56 +08:00
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#define rv_floatreg_t rt_int64_t
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2020-11-20 12:05:37 +08:00
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#endif
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#ifdef ARCH_RISCV_FPU_S
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#define FSTORE fsw
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#define FLOAD flw
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#define FREGBYTES 4
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2021-03-27 17:51:56 +08:00
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#define rv_floatreg_t rt_int32_t
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2020-11-20 12:05:37 +08:00
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#endif
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#endif
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2018-12-08 10:41:38 +08:00
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#endif
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