107 lines
3.7 KiB
C
107 lines
3.7 KiB
C
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/*
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* Copyright (c) 2006-2021, JuiceVm Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021/04/22 Juice the first version
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*/
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#ifndef __RV_CONFIG_H__
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#define __RV_CONFIG_H__
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#define RV64I_SUPPORT_ENBALE
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#define RV64_MMU_ENBALE 1
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#define RV_ENDLESS_LOOP_CHECK_ENBALE 1
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#if defined(RV_ENDLESS_LOOP_CHECK_ENBALE) && RV_ENDLESS_LOOP_CHECK_ENBALE == 1
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#define RV_ENDLESS_LOOP_CHECK_BUF_SIZE (30)
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#define RV_ENDLESS_LOOP_CHECK_EXIT_CNT (3)
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#define RV_ENDLESS_LOOP_CHECK_MD5_HASH 1
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#endif
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// #define RISCV_ANGEL_ONLY
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#define Machine_Mode_SUPPORT
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#define Supervisor_Mode_SUPPORT
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// #define User_Mode_SUPPORT
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// #define Hypervisor_Mode_SUPPORT
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#define ATOMIC_Module_SUPPORT
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#define RV_CPU_CSR_DEF_Vendor_ID 0
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#define RV_CPU_CSR_DEF_March_ID 0
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#define RV_CPU_CSR_DEF_Mimp_ID 0
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#define RV_CPU_CSR_DEF_Mhart_ID 0
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#define JUICE_VM_LOG_MAX_NUM (600)
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#define JUICE_VM_INC_CHANGELOG 0
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#define RAM_SIZE_KB (1024)
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#define RAM_SIZE_MB (1024*RAM_SIZE_KB)
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#define RV_CPU_SIM_RAM_START_ADDR (0x80000000)
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#define RV_CPU_SIM_RAM_SIZE (300 * RAM_SIZE_MB)
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#define RV_CPU_SIM_CAUSETABLE_MAX_NUM 100//MXLEN-1 bit
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#define RV_CPU_SIM_PERDEV_NUM 50
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#define rv_peripheral_device_add_check_dev 1
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// | MXLEN-1 MXLEN-2 | MXLEN-3 26| 25 0 |
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// | MXL[1:0](WARL) | WLRL | Extensions[25:0] (WARL) |
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// | 2 | MXLEN-28 | 26 |
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// Figure 3.1: Machine ISA register (misa).
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// Bit | Character | Description
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// 0 | A | Atomic extension
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// 1 | B | Tentatively reserved for Bit-Manipulation extension
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// 2 | C | Compressed extension
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// 3 | D | Double-precision floating-point extension
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// 4 | E | RV32E base ISA
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// 5 | F | Single-precision floating-point extension
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// 6 | G | Reserved
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// 7 | H | Hypervisor extension
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// 8 | I | RV32I/64I/128I base ISA
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// 9 | J | Tentatively reserved for Dynamically Translated Languages extension
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// 10 | K | Reserved
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// 11 | L | Tentatively reserved for Decimal Floating-Point extension
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// 12 | M | Integer Multiply/Divide extension
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// 13 | N | User-level interrupts supported
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// 14 | O | Reserved
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// 15 | P | Tentatively reserved for Packed-SIMD extension
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// 16 | Q | Quad-precision floating-point extension
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// 17 | R | Reserved
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// 18 | S | Supervisor mode implemented
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// 19 | T | Tentatively reserved for Transactional Memory extension
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// 20 | U | User mode implemented
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// 21 | V | Tentatively reserved for Vector extension
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// 22 | W | Reserved
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// 23 | X | Non-standard extensions present
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// 24 | Y | Reserved
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// 25 | Z | Reserved
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#define RV_MISA_ATOMIC_EXT (1<<0)
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#define RV_MISA_INTEGER_EXT (1<<8)
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#define RV_MISA_UMODE_INT_EXT (1<<13)
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#define RV_MISA_SMODE_IMP_EXT (1<<18)
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#define RV_MISA_UMODE_IMP_EXT (1<<20)
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// | MXL | XLEN |
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// | 1 | 32 |
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// | 2 | 64 |
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// | 3 | 128 |
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#define RV_MISA_XLEN_32 (1<<(32-2))
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#define RV_MISA_XLEN_64 (uint64_t)((uint64_t)(2)<<(64-2))
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// #define RV_MISA_XLEN_128 ((uint128_t)(3)<<(128-2))
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#define RV_MISA_CSR_REGISTER ((uint64_t)(RV_MISA_XLEN_64 | RV_MISA_ATOMIC_EXT | RV_MISA_INTEGER_EXT /*| RV_MISA_UMODE_INT_EXT*/ | RV_MISA_SMODE_IMP_EXT /*| RV_MISA_UMODE_IMP_EXT*/))
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#endif // __RV_CONFIG_H__
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