2019-02-16 12:42:19 +08:00
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/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018-11-5 SummerGift change to new framework
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*/
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#ifndef __BOARD_H__
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#define __BOARD_H__
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#include <rtthread.h>
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#include <stm32l4xx.h>
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#include "drv_common.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef BSP_USING_GPIO
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#include "drv_gpio.h"
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/* Board Pin definitions */
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#define LED1_PIN GET_PIN(B, 6)
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#define LED2_PIN GET_PIN(E, 3)
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#define LED3_PIN GET_PIN(D, 15)
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#define KEY1_PIN GET_PIN(E, 11)
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#define KEY2_PIN GET_PIN(E, 14)
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#define KEY3_PIN GET_PIN(E, 10)
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#endif /* BSP_USING_GPIO */
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/* Internal SRAM memory size[Kbytes] <8-64>, Default: 64*/
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#define STM32_SRAM_SIZE 320
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#define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024)
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#define STM32_FLASH_START_ADRESS ((uint32_t)0x08000000)
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#define STM32_FLASH_SIZE (1024 * 1024)
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#define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE))
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2019-05-06 10:20:58 +08:00
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#if defined(__CC_ARM) || defined(__CLANG_ARM)
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2019-02-16 12:42:19 +08:00
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extern int Image$$RW_IRAM1$$ZI$$Limit;
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#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
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#elif __ICCARM__
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#pragma section="CSTACK"
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#define HEAP_BEGIN (__segment_end("CSTACK"))
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#else
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extern int __bss_end;
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#define HEAP_BEGIN ((void *)&__bss_end)
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#endif
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#define HEAP_END STM32_SRAM_END
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void SystemClock_Config(void);
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#ifdef __cplusplus
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}
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#endif
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#endif
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