440 lines
11 KiB
C
440 lines
11 KiB
C
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/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-08-28 qiyu first version
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*/
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#include <rthw.h>
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#include "drv_gpio.h"
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#include "F2837xD_device.h"
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#include "F28x_Project.h" // Device Headerfile and Examples Include File
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#ifdef RT_USING_PIN
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// the gpio pin number for each port is 32, while it is 16 for ARM
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#define PIN_NUM(port, no) (((((port) & 0xFu) << 5) | ((no) & 0x1F)))
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#define PIN_PORT(pin) ((rt_uint16_t)(((pin) >> 5) & 0xFu))
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#define PIN_NO(pin) ((rt_uint16_t)((pin) & 0x1Fu))
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#define PIN_c28x_PORT(pin) (volatile Uint32 *)&GpioDataRegs + (PIN_PORT(pin))*GPY_DATA_OFFSET
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#define PIN_c28x_PIN(pin) ((rt_uint32_t)(1u << PIN_NO(pin)))
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#define PIN_c28x_PORT_MAX 6 /* gpioA to GPIOF in total*/
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#define PIN_IRQ_MAX 5 /* XINT1 to XINT5 in total */
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static rt_err_t c28x_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
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rt_uint32_t mode, void (*hdr)(void *args), void *args);
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static rt_err_t c28x_pin_dettach_irq(struct rt_device *device, rt_int32_t pin);
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static rt_err_t c28x_pin_irq_enable(struct rt_device *device, rt_base_t pin,
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rt_uint32_t enabled);
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static rt_base_t c28x_pin_get(const char *name)
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{
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int hw_pin_num = 0;
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int i, name_len;
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name_len = rt_strlen(name);
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if ((name_len < 3) || (name_len >= 7))
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{
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return -RT_EINVAL;
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}
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/*
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* PX.y
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*/
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if ((name[0] != 'P') || (name[2] != '.'))
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{
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return -RT_EINVAL;
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}
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for (i = 3; i < name_len; i++)
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{
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hw_pin_num *= 10;
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hw_pin_num += name[i] - '0';
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}
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return hw_pin_num;
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}
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static void c28x_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
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{
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volatile Uint32 *gpioDataReg;
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Uint32 pinMask;
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if (PIN_PORT(pin) < PIN_c28x_PORT_MAX)
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{
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gpioDataReg = PIN_c28x_PORT(pin);
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pinMask = 1UL << (PIN_NO(pin));
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if (value == 0)
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{
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gpioDataReg[GPYCLEAR] = pinMask;
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}
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else
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{
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gpioDataReg[GPYSET] = pinMask;
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}
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}
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}
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static int c28x_pin_read(rt_device_t dev, rt_base_t pin)
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{
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volatile Uint32 *gpioDataReg;
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int value = PIN_LOW;
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if (PIN_PORT(pin) < PIN_c28x_PORT_MAX)
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{
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gpioDataReg = PIN_c28x_PORT(pin);
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value = (gpioDataReg[GPYDAT] >> PIN_NO(pin)) & 0x1;
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}
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return value;
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}
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static void c28x_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
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{
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volatile Uint32 *gpioBaseAddr;
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volatile Uint32 *dir, *pud, *odr;
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if (PIN_PORT(pin) >= PIN_c28x_PORT_MAX)
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{
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return;
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}
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rt_uint32_t pinMask;
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pinMask = 1UL << PIN_NO(pin);
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gpioBaseAddr = (Uint32 *)&GpioCtrlRegs + (PIN_PORT(pin))*GPY_CTRL_OFFSET;
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dir = gpioBaseAddr + GPYDIR;
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pud = gpioBaseAddr + GPYPUD;
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odr = gpioBaseAddr + GPYODR;
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EALLOW;
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if (mode == PIN_MODE_OUTPUT)
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{
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*dir |= pinMask;
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}
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else if (mode == PIN_MODE_INPUT)
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{
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*dir &= ~pinMask;
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}
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else if (mode == PIN_MODE_INPUT_PULLUP)
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{
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*dir &= ~pinMask;
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*pud &= ~pinMask;
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}
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else if (mode == PIN_MODE_INPUT_PULLDOWN)
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{
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/* input setting: pull down. */
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*dir &= ~pinMask;
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*pud |= pinMask;
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}
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else if (mode == PIN_MODE_OUTPUT_OD)
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{
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/* output setting: od. */
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*dir |= pinMask;
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*odr |= pinMask;
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}
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EDIS;
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}
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const static struct rt_pin_ops _c28x_pin_ops =
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{
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c28x_pin_mode,
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c28x_pin_write,
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c28x_pin_read,
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c28x_pin_attach_irq,
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c28x_pin_dettach_irq,
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c28x_pin_irq_enable,
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c28x_pin_get,
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};
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int rt_hw_pin_init(void)
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{
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return rt_device_pin_register("pin", &_c28x_pin_ops, RT_NULL);
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}
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static struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
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{
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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};
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static rt_int16_t pin_irq_xint_tab[] =
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{
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BSP_XINT1_PIN,
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BSP_XINT2_PIN,
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BSP_XINT3_PIN,
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BSP_XINT4_PIN,
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BSP_XINT5_PIN
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};
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rt_inline rt_int32_t get_irq_index(rt_uint32_t pin)
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{
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int i;
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for(i = 0 ; i < PIN_IRQ_MAX ; i++)
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{
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if(pin_irq_xint_tab[i] == pin)
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{
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return i;
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}
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}
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return -1;
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}
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#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
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static rt_err_t c28x_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
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rt_uint32_t mode, void (*hdr)(void *args), void *args)
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{
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rt_base_t level;
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rt_int32_t irqindex = -1;
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if (PIN_PORT(pin) >= PIN_c28x_PORT_MAX)
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{
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return -RT_ENOSYS;
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}
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irqindex = get_irq_index(pin);
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level = rt_hw_interrupt_disable();
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if (pin_irq_hdr_tab[irqindex].pin == pin &&
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pin_irq_hdr_tab[irqindex].hdr == hdr &&
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pin_irq_hdr_tab[irqindex].mode == mode &&
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pin_irq_hdr_tab[irqindex].args == args)
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{
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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if (pin_irq_hdr_tab[irqindex].pin != -1)
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{
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rt_hw_interrupt_enable(level);
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return -RT_EBUSY;
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}
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pin_irq_hdr_tab[irqindex].pin = pin;
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pin_irq_hdr_tab[irqindex].hdr = hdr;
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pin_irq_hdr_tab[irqindex].mode = mode;
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pin_irq_hdr_tab[irqindex].args = args;
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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static rt_err_t c28x_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
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{
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rt_base_t level;
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rt_int32_t irqindex = -1;
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rt_uint16_t i;
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if (PIN_PORT(pin) >= PIN_c28x_PORT_MAX)
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{
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return -RT_ENOSYS;
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}
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for(i = 0 ; i < PIN_IRQ_MAX ; i++)
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{
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if(pin_irq_hdr_tab[i].pin == pin)
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{
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irqindex = i;
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break;
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}
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}
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if (irqindex == -1)
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{
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return -RT_ENOSYS;
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}
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level = rt_hw_interrupt_disable();
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pin_irq_hdr_tab[irqindex].pin = -1;
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pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
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pin_irq_hdr_tab[irqindex].mode = 0;
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pin_irq_hdr_tab[irqindex].args = RT_NULL;
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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static rt_err_t c28x_pin_irq_enable(struct rt_device *device, rt_base_t pin,
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rt_uint32_t enabled)
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{
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rt_base_t level;
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rt_int32_t irqindex = -1;
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rt_uint16_t channel;
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rt_uint16_t edge_mode,pin_mode;
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if (PIN_PORT(pin) >= PIN_c28x_PORT_MAX)
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{
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return -RT_ENOSYS;
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}
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irqindex = get_irq_index(pin);
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/* irqindex+1 = channel*/
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if (irqindex < 0 || irqindex >= PIN_IRQ_MAX)
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{
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return -RT_ENOSYS;
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}
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if (enabled == PIN_IRQ_ENABLE)
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{
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level = rt_hw_interrupt_disable();
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if (pin_irq_hdr_tab[irqindex].pin == -1)
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{
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rt_hw_interrupt_enable(level);
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return -RT_ENOSYS;
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}
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/*
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* 1. set the edge mode of interrupt triggering
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* 2. set the GPIO mode
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* 3. enable XINT channel and set the input source
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*/
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channel = irqindex+1;
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switch (pin_irq_hdr_tab[irqindex].mode)
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{
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case PIN_IRQ_MODE_RISING:
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edge_mode = 1;
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pin_mode = PIN_MODE_INPUT_PULLDOWN;
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break;
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case PIN_IRQ_MODE_FALLING:
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edge_mode = 0;
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pin_mode = PIN_MODE_INPUT_PULLUP;
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break;
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case PIN_IRQ_MODE_RISING_FALLING:
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edge_mode = 3;
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pin_mode = PIN_MODE_INPUT;
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break;
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}
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if(channel == 1)
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{
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XintRegs.XINT1CR.bit.ENABLE = 1; // Enable XINT1
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EALLOW;
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InputXbarRegs.INPUT4SELECT = pin; //Set XINT1 source to GPIO-pin
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EDIS;
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XintRegs.XINT1CR.bit.POLARITY = edge_mode; // Falling edge interrupt
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}
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else if(channel == 2)
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{
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XintRegs.XINT2CR.bit.ENABLE = 1; // Enable XINT2
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EALLOW;
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InputXbarRegs.INPUT5SELECT = pin; //Set XINT1 source to GPIO-pin
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EDIS;
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XintRegs.XINT2CR.bit.POLARITY = edge_mode; // Falling edge interrupt
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}
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else if(channel == 3)
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{
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XintRegs.XINT3CR.bit.ENABLE = 1; // Enable XINT2
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EALLOW;
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InputXbarRegs.INPUT6SELECT = pin; //Set XINT1 source to GPIO-pin
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EDIS;
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XintRegs.XINT3CR.bit.POLARITY = edge_mode; // Falling edge interrupt
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}
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else if(channel == 4)
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{
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XintRegs.XINT4CR.bit.ENABLE = 1; // Enable XINT2
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EALLOW;
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InputXbarRegs.INPUT13SELECT = pin; //Set XINT1 source to GPIO-pin
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EDIS;
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XintRegs.XINT4CR.bit.POLARITY = edge_mode; // Falling edge interrupt
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}
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else if(channel == 5)
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{
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XintRegs.XINT5CR.bit.ENABLE = 1; // Enable XINT2
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EALLOW;
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InputXbarRegs.INPUT14SELECT = pin; //Set XINT1 source to GPIO-pin
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EDIS;
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XintRegs.XINT5CR.bit.POLARITY = edge_mode; // Falling edge interrupt
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}
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c28x_pin_mode(device, pin, pin_mode);
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rt_hw_interrupt_enable(level);
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}
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else if (enabled == PIN_IRQ_DISABLE)
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{
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level = rt_hw_interrupt_disable();
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channel = irqindex+1;
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/*
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* TODO modify this simpler
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*/
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if(channel == 1)
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{
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XintRegs.XINT1CR.bit.ENABLE = 0; // Disable XINT1
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}
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else if(channel == 2)
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{
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XintRegs.XINT2CR.bit.ENABLE = 0; // Disable XINT2
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}
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else if(channel == 3)
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{
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XintRegs.XINT3CR.bit.ENABLE = 0; // Disable XINT2
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}
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else if(channel == 4)
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{
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XintRegs.XINT4CR.bit.ENABLE = 0; // Disable XINT2
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}
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else if(channel == 5)
|
||
|
|
{
|
||
|
|
XintRegs.XINT5CR.bit.ENABLE = 0; // Disable XINT2
|
||
|
|
}
|
||
|
|
rt_hw_interrupt_enable(level);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
return -RT_ENOSYS;
|
||
|
|
}
|
||
|
|
|
||
|
|
return RT_EOK;
|
||
|
|
}
|
||
|
|
|
||
|
|
void GPIO_XINT_Callback(rt_int16_t XINT_number);
|
||
|
|
|
||
|
|
interrupt void XINT1_Handler(void)
|
||
|
|
{
|
||
|
|
rt_interrupt_enter();
|
||
|
|
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
|
||
|
|
GPIO_XINT_Callback(1);
|
||
|
|
rt_interrupt_leave();
|
||
|
|
}
|
||
|
|
|
||
|
|
interrupt void XINT2_Handler(void)
|
||
|
|
{
|
||
|
|
rt_interrupt_enter();
|
||
|
|
GPIO_XINT_Callback(2);
|
||
|
|
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
|
||
|
|
rt_interrupt_leave();
|
||
|
|
}
|
||
|
|
|
||
|
|
interrupt void XINT3_Handler(void)
|
||
|
|
{
|
||
|
|
rt_interrupt_enter();
|
||
|
|
GPIO_XINT_Callback(3);
|
||
|
|
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
|
||
|
|
rt_interrupt_leave();
|
||
|
|
}
|
||
|
|
|
||
|
|
interrupt void XINT4_Handler(void)
|
||
|
|
{
|
||
|
|
rt_interrupt_enter();
|
||
|
|
GPIO_XINT_Callback(4);
|
||
|
|
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
|
||
|
|
rt_interrupt_leave();
|
||
|
|
}
|
||
|
|
|
||
|
|
interrupt void XINT5_Handler(void)
|
||
|
|
{
|
||
|
|
rt_interrupt_enter();
|
||
|
|
GPIO_XINT_Callback(5);
|
||
|
|
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
|
||
|
|
rt_interrupt_leave();
|
||
|
|
}
|
||
|
|
|
||
|
|
void GPIO_XINT_Callback(rt_int16_t XINT_number)
|
||
|
|
{
|
||
|
|
rt_int32_t irqindex = XINT_number - 1;
|
||
|
|
if(pin_irq_hdr_tab[irqindex].hdr)
|
||
|
|
{
|
||
|
|
pin_irq_hdr_tab[irqindex].hdr(pin_irq_hdr_tab[irqindex].args);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif /* RT_USING_PIN */
|
||
|
|
|
||
|
|
|
||
|
|
|