2022-05-06 09:28:21 +08:00
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/*
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2022-05-31 11:53:56 +08:00
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* Copyright (c) 2006-2022, RT-Thread Development Team
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* Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd.
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2022-05-06 09:28:21 +08:00
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-04-28 CDT first version
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*/
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#ifndef __DRV_ETH_H__
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#define __DRV_ETH_H__
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/*******************************************************************************
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* Include files
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******************************************************************************/
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#include <rtthread.h>
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#include <rthw.h>
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#include <rtdevice.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* The PHY basic control register */
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#define PHY_BASIC_CONTROL_REG 0x00U
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#define PHY_RESET_MASK (1<<15)
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#define PHY_AUTO_NEGOTIATION_MASK (1<<12)
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/* The PHY basic status register */
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#define PHY_BASIC_STATUS_REG 0x01U
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#define PHY_LINKED_STATUS_MASK (1<<2)
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#define PHY_AUTONEGO_COMPLETE_MASK (1<<5)
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/* The PHY ID one register */
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#define PHY_ID1_REG 0x02U
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#ifdef PHY_USING_RTL8201F
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/* Extended PHY Registers */
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#define PHY_PSMR (0x18U) /*!< Power Saving Mode Register */
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#define PHY_IISDR (0x1EU) /*!< Interrupt Indicators and SNR Display Register */
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#define PHY_PSR (0x1FU) /*!< Page Select Register */
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#define PHY_P7_RMSR (0x10U) /*!< RMII Mode Setting Register */
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#define PHY_P7_IWLFR (0x13U) /*!< Interrupt, WOL Enable, and LED Function Registers */
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/* The following parameters will return to default values after a software reset */
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#define PHY_EN_PWR_SAVE (0x8000U) /*!< Enable Power Saving Mode */
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#define PHY_FLAG_AUTO_NEGO_ERROR (0x8000U) /*!< Auto-Negotiation Error Interrupt Flag */
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#define PHY_FLAG_SPEED_MODE_CHANGE (0x4000U) /*!< Speed Mode Change Interrupt Flag */
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#define PHY_FLAG_DUPLEX_MODE_CHANGE (0x2000U) /*!< Duplex Mode Change Interrupt Flag */
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#define PHY_FLAG_LINK_STATUS_CHANGE (0x0800U) /*!< Link Status Change Interrupt Flag */
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#define PHY_PAGE_ADDR_0 (0x0000U) /*!< Page Address 0 (default) */
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#define PHY_PAGE_ADDR_7 (0x0007U) /*!< Page Address 7 */
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#define PHY_RMII_CLK_DIR (0x1000U) /*!< TXC direction in RMII Mode */
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#define PHY_RMII_MODE (0x0008U) /*!< RMII Mode or MII Mode */
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#define PHY_RMII_RXDV_CRSDV (0x0004U) /*!< CRS_DV or RXDV select */
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#define PHY_INT_LINK_CHANGE (0x2000U) /*!< Link Change Interrupt Mask */
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#define PHY_INT_DUPLEX_CHANGE (0x1000U) /*!< Duplex Change Interrupt Mask */
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#define PHY_INT_AUTO_NEGO_ERROR (0x0800U) /*!< Auto-Negotiation Error Interrupt Mask */
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#define PHY_LED_WOL_SELECT (0x0400U) /*!< LED and Wake-On-LAN Function Selection */
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#define PHY_LED_SELECT (0x0030U) /*!< Traditional LED Function Selection. */
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#define PHY_LED_SELECT_00 (0x0000U) /*!< LED0: ACT(all) LED1: LINK(100) */
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#define PHY_LED_SELECT_01 (0x0010U) /*!< LED0: LINK(ALL)/ACT(all) LED1: LINK(100) */
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#define PHY_LED_SELECT_10 (0x0020U) /*!< LED0: LINK(10)/ACT(all) LED1: LINK(100) */
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#define PHY_LED_SELECT_11 (0x0030U) /*!< LED0: LINK(10)/ACT(10) LED1: LINK(100)/ACT(100) */
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#define PHY_EN_10M_LED_FUNC (0x0001U) /*!< Enable 10M LPI LED Function */
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* __DRV_ETH_H__ */
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