2021-05-13 16:33:40 +08:00
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/*
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* Copyright (C) 2007 - 2019 Xilinx, Inc.
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* Copyright (C) 2021 WangHuachen.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
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* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
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* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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* OF SUCH DAMAGE.
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*
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* This file is part of the lwIP TCP/IP stack.
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*
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*/
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#include "lwipopts.h"
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#include "xlwipconfig.h"
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#include "xemac_ieee_reg.h"
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#if !NO_SYS
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#ifdef OS_IS_XILKERNEL
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#include "xmk.h"
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#include "sys/process.h"
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#endif
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#endif
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#include "lwip/mem.h"
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#include "lwip/stats.h"
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#include "lwip/sys.h"
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#include "lwip/ip.h"
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#include "lwip/tcp.h"
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#include "lwip/udp.h"
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#include "lwip/priv/tcp_priv.h"
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#include "netif/etharp.h"
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#include "netif/xadapter.h"
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#ifdef XLWIP_CONFIG_INCLUDE_EMACLITE
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#include "netif/xemacliteif.h"
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#endif
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#ifdef XLWIP_CONFIG_INCLUDE_AXI_ETHERNET
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#include "netif/xaxiemacif.h"
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#endif
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#ifdef XLWIP_CONFIG_INCLUDE_GEM
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#include "netif/xemacpsif.h"
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#endif
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#if !NO_SYS
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#include "lwip/tcpip.h"
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#endif
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#ifdef OS_IS_FREERTOS
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#define THREAD_STACKSIZE 256
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#define LINK_DETECT_THREAD_INTERVAL 1000 /* one second */
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void link_detect_thread(void *p);
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#endif
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/* global lwip debug variable used for debugging */
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int lwip_runtime_debug = 0;
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enum ethernet_link_status eth_link_status = ETH_LINK_UNDEFINED;
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u32_t phyaddrforemac;
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void
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lwip_raw_init()
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{
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2021-05-14 14:42:21 +08:00
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ip_init(); /* Doesn't do much, it should be called to handle future changes. */
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2021-05-13 16:33:40 +08:00
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#if LWIP_UDP
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2021-05-14 14:42:21 +08:00
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udp_init(); /* Clears the UDP PCB list. */
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2021-05-13 16:33:40 +08:00
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#endif
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#if LWIP_TCP
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2021-05-14 14:42:21 +08:00
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tcp_init(); /* Clears the TCP PCB list and clears some internal TCP timers. */
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/* Note: you must call tcp_fasttmr() and tcp_slowtmr() at the */
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/* predefined regular intervals after this initialization. */
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2021-05-13 16:33:40 +08:00
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#endif
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}
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static enum xemac_types
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find_mac_type(unsigned base)
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{
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2021-05-14 14:22:23 +08:00
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int i;
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2021-05-13 16:33:40 +08:00
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2021-05-14 14:22:23 +08:00
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for (i = 0; i < xtopology_n_emacs; i++) {
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2021-05-14 14:42:21 +08:00
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if (xtopology[i].emac_baseaddr == base)
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return xtopology[i].emac_type;
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}
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2021-05-13 16:33:40 +08:00
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2021-05-14 14:22:23 +08:00
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return xemac_type_unknown;
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2021-05-13 16:33:40 +08:00
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}
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int
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xtopology_find_index(unsigned base)
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{
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2021-05-14 14:22:23 +08:00
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int i;
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2021-05-13 16:33:40 +08:00
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2021-05-14 14:22:23 +08:00
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for (i = 0; i < xtopology_n_emacs; i++) {
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2021-05-14 14:42:21 +08:00
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if (xtopology[i].emac_baseaddr == base)
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return i;
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}
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2021-05-13 16:33:40 +08:00
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2021-05-14 14:22:23 +08:00
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return -1;
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2021-05-13 16:33:40 +08:00
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}
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/*
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* xemac_add: this is a wrapper around lwIP's netif_add function.
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* The objective is to provide portability between the different Xilinx MAC's
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* This function can be used to add both xps_ethernetlite and xps_ll_temac
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* based interfaces
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*/
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struct netif *
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xemac_add(struct netif *netif,
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2021-05-14 14:22:23 +08:00
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ip_addr_t *ipaddr, ip_addr_t *netmask, ip_addr_t *gw,
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unsigned char *mac_ethernet_address,
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unsigned mac_baseaddr)
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2021-05-13 16:33:40 +08:00
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{
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2021-05-14 14:22:23 +08:00
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int i;
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2021-05-13 16:33:40 +08:00
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#ifdef OS_IS_FREERTOS
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2021-05-14 14:42:21 +08:00
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/* Start thread to detect link periodically for Hot Plug autodetect */
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2021-05-14 14:22:23 +08:00
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sys_thread_new("link_detect_thread", link_detect_thread, netif,
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2021-05-14 14:42:21 +08:00
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THREAD_STACKSIZE, tskIDLE_PRIORITY);
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2021-05-13 16:33:40 +08:00
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#endif
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2021-05-14 14:42:21 +08:00
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/* set mac address */
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2021-05-14 14:22:23 +08:00
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netif->hwaddr_len = 6;
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for (i = 0; i < 6; i++)
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2021-05-14 14:42:21 +08:00
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netif->hwaddr[i] = mac_ethernet_address[i];
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2021-05-13 16:33:40 +08:00
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2021-05-14 14:42:21 +08:00
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/* initialize based on MAC type */
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switch (find_mac_type(mac_baseaddr)) {
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case xemac_type_xps_emaclite:
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2021-05-13 16:33:40 +08:00
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#ifdef XLWIP_CONFIG_INCLUDE_EMACLITE
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2021-05-14 14:42:21 +08:00
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return netif_add(netif, ipaddr, netmask, gw,
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(void*)(UINTPTR)mac_baseaddr,
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xemacliteif_init,
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2021-05-13 16:33:40 +08:00
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#if NO_SYS
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2021-05-14 14:42:21 +08:00
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ethernet_input
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2021-05-13 16:33:40 +08:00
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#else
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2021-05-14 14:42:21 +08:00
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tcpip_input
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2021-05-13 16:33:40 +08:00
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#endif
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2021-05-14 14:42:21 +08:00
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);
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2021-05-13 16:33:40 +08:00
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#else
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2021-05-14 14:42:21 +08:00
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return NULL;
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2021-05-13 16:33:40 +08:00
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#endif
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2021-05-14 14:42:21 +08:00
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case xemac_type_axi_ethernet:
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2021-05-13 16:33:40 +08:00
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#ifdef XLWIP_CONFIG_INCLUDE_AXI_ETHERNET
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2021-05-14 14:42:21 +08:00
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return netif_add(netif, ipaddr, netmask, gw,
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(void*)(UINTPTR)mac_baseaddr,
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xaxiemacif_init,
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2021-05-13 16:33:40 +08:00
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#if NO_SYS
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2021-05-14 14:42:21 +08:00
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ethernet_input
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2021-05-13 16:33:40 +08:00
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#else
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2021-05-14 14:42:21 +08:00
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tcpip_input
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2021-05-13 16:33:40 +08:00
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#endif
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2021-05-14 14:42:21 +08:00
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);
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2021-05-13 16:33:40 +08:00
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#else
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2021-05-14 14:42:21 +08:00
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return NULL;
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2021-05-13 16:33:40 +08:00
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#endif
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#if defined (__arm__) || defined (__aarch64__)
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2021-05-14 14:42:21 +08:00
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case xemac_type_emacps:
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2021-05-13 16:33:40 +08:00
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#ifdef XLWIP_CONFIG_INCLUDE_GEM
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2021-05-14 14:42:21 +08:00
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return netif_add(netif, ipaddr, netmask, gw,
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(void*)(UINTPTR)mac_baseaddr,
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xemacpsif_init,
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2021-05-13 16:33:40 +08:00
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#if NO_SYS
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2021-05-14 14:42:21 +08:00
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ethernet_input
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2021-05-13 16:33:40 +08:00
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#else
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2021-05-14 14:42:21 +08:00
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tcpip_input
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2021-05-13 16:33:40 +08:00
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#endif
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2021-05-14 14:42:21 +08:00
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);
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2021-05-13 16:33:40 +08:00
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#endif
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#endif
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2021-05-14 14:42:21 +08:00
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default:
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xil_printf("unable to determine type of EMAC with baseaddress 0x%08x\r\n",
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mac_baseaddr);
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return NULL;
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}
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2021-05-13 16:33:40 +08:00
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}
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int
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xemacif_input(struct netif *netif)
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{
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2021-05-14 14:22:23 +08:00
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struct xemac_s *emac = (struct xemac_s *)netif->state;
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2021-05-13 16:33:40 +08:00
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2021-05-14 14:22:23 +08:00
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int n_packets = 0;
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2021-05-13 16:33:40 +08:00
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2021-05-14 14:22:23 +08:00
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switch (emac->type) {
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2021-05-14 14:42:21 +08:00
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case xemac_type_xps_emaclite:
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2021-05-13 16:33:40 +08:00
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#ifdef XLWIP_CONFIG_INCLUDE_EMACLITE
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2021-05-14 14:42:21 +08:00
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n_packets = xemacliteif_input(netif);
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break;
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2021-05-13 16:33:40 +08:00
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#else
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2021-05-14 14:42:21 +08:00
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// print("incorrect configuration: xps_ethernetlite drivers not present?");
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while(1);
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return 0;
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2021-05-13 16:33:40 +08:00
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#endif
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2021-05-14 14:42:21 +08:00
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case xemac_type_axi_ethernet:
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2021-05-13 16:33:40 +08:00
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#ifdef XLWIP_CONFIG_INCLUDE_AXI_ETHERNET
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2021-05-14 14:42:21 +08:00
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n_packets = xaxiemacif_input(netif);
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break;
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2021-05-13 16:33:40 +08:00
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#else
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2021-05-14 14:42:21 +08:00
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// print("incorrect configuration: axi_ethernet drivers not present?");
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while(1);
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return 0;
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2021-05-13 16:33:40 +08:00
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#endif
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#if defined (__arm__) || defined (__aarch64__)
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2021-05-14 14:42:21 +08:00
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case xemac_type_emacps:
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2021-05-13 16:33:40 +08:00
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#ifdef XLWIP_CONFIG_INCLUDE_GEM
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2021-05-14 14:42:21 +08:00
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n_packets = xemacpsif_input(netif);
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break;
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2021-05-13 16:33:40 +08:00
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#else
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2021-05-14 14:42:21 +08:00
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xil_printf("incorrect configuration: ps7_ethernet drivers not present?\r\n");
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while(1);
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return 0;
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2021-05-13 16:33:40 +08:00
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#endif
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#endif
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2021-05-14 14:42:21 +08:00
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default:
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// print("incorrect configuration: unknown temac type");
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while(1);
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return 0;
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}
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2021-05-13 16:33:40 +08:00
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2021-05-14 14:22:23 +08:00
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return n_packets;
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2021-05-13 16:33:40 +08:00
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}
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#if defined(XLWIP_CONFIG_INCLUDE_GEM)
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u32_t phy_link_detect(XEmacPs *xemacp, u32_t phy_addr)
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{
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2021-05-14 14:22:23 +08:00
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u16_t status;
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2021-05-13 16:33:40 +08:00
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2021-05-14 14:42:21 +08:00
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/* Read Phy Status register twice to get the confirmation of the current
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* link status.
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*/
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2021-05-14 14:22:23 +08:00
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XEmacPs_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
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XEmacPs_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
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2021-05-13 16:33:40 +08:00
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2021-05-14 14:22:23 +08:00
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if (status & IEEE_STAT_LINK_STATUS)
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2021-05-14 14:42:21 +08:00
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return 1;
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2021-05-14 14:22:23 +08:00
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return 0;
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2021-05-13 16:33:40 +08:00
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}
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#elif defined(XLWIP_CONFIG_INCLUDE_AXI_ETHERNET)
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static u32_t phy_link_detect(XAxiEthernet *xemacp, u32_t phy_addr)
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{
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2021-05-14 14:22:23 +08:00
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u16_t status;
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2021-05-13 16:33:40 +08:00
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2021-05-14 14:42:21 +08:00
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/* Read Phy Status register twice to get the confirmation of the current
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* link status.
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*/
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2021-05-14 14:22:23 +08:00
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XAxiEthernet_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
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XAxiEthernet_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
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2021-05-13 16:33:40 +08:00
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2021-05-14 14:22:23 +08:00
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if (status & IEEE_STAT_LINK_STATUS)
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2021-05-14 14:42:21 +08:00
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return 1;
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2021-05-14 14:22:23 +08:00
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return 0;
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2021-05-13 16:33:40 +08:00
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}
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#elif defined(XLWIP_CONFIG_INCLUDE_EMACLITE)
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static u32_t phy_link_detect(XEmacLite *xemacp, u32_t phy_addr)
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{
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2021-05-14 14:22:23 +08:00
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u16_t status;
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2021-05-13 16:33:40 +08:00
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2021-05-14 14:42:21 +08:00
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/* Read Phy Status register twice to get the confirmation of the current
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* link status.
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*/
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2021-05-14 14:22:23 +08:00
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XEmacLite_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
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|
|
XEmacLite_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
|
2021-05-13 16:33:40 +08:00
|
|
|
|
2021-05-14 14:22:23 +08:00
|
|
|
if (status & IEEE_STAT_LINK_STATUS)
|
2021-05-14 14:42:21 +08:00
|
|
|
return 1;
|
2021-05-14 14:22:23 +08:00
|
|
|
return 0;
|
2021-05-13 16:33:40 +08:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#if defined(XLWIP_CONFIG_INCLUDE_GEM)
|
|
|
|
u32_t phy_autoneg_status(XEmacPs *xemacp, u32_t phy_addr)
|
|
|
|
{
|
2021-05-14 14:22:23 +08:00
|
|
|
u16_t status;
|
2021-05-13 16:33:40 +08:00
|
|
|
|
2021-05-14 14:42:21 +08:00
|
|
|
/* Read Phy Status register twice to get the confirmation of the current
|
|
|
|
* link status.
|
|
|
|
*/
|
2021-05-14 14:22:23 +08:00
|
|
|
XEmacPs_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
|
|
|
|
XEmacPs_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
|
2021-05-13 16:33:40 +08:00
|
|
|
|
2021-05-14 14:22:23 +08:00
|
|
|
if (status & IEEE_STAT_AUTONEGOTIATE_COMPLETE)
|
2021-05-14 14:42:21 +08:00
|
|
|
return 1;
|
2021-05-14 14:22:23 +08:00
|
|
|
return 0;
|
2021-05-13 16:33:40 +08:00
|
|
|
}
|
|
|
|
#elif defined(XLWIP_CONFIG_INCLUDE_AXI_ETHERNET)
|
|
|
|
static u32_t phy_autoneg_status(XAxiEthernet *xemacp, u32_t phy_addr)
|
|
|
|
{
|
2021-05-14 14:22:23 +08:00
|
|
|
u16_t status;
|
2021-05-13 16:33:40 +08:00
|
|
|
|
2021-05-14 14:42:21 +08:00
|
|
|
/* Read Phy Status register twice to get the confirmation of the current
|
|
|
|
* link status.
|
|
|
|
*/
|
2021-05-14 14:22:23 +08:00
|
|
|
XAxiEthernet_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
|
|
|
|
XAxiEthernet_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
|
2021-05-13 16:33:40 +08:00
|
|
|
|
2021-05-14 14:22:23 +08:00
|
|
|
if (status & IEEE_STAT_AUTONEGOTIATE_COMPLETE)
|
2021-05-14 14:42:21 +08:00
|
|
|
return 1;
|
2021-05-14 14:22:23 +08:00
|
|
|
return 0;
|
2021-05-13 16:33:40 +08:00
|
|
|
}
|
|
|
|
#elif defined(XLWIP_CONFIG_INCLUDE_EMACLITE)
|
|
|
|
static u32_t phy_autoneg_status(XEmacLite *xemacp, u32_t phy_addr)
|
|
|
|
{
|
2021-05-14 14:22:23 +08:00
|
|
|
u16_t status;
|
2021-05-13 16:33:40 +08:00
|
|
|
|
2021-05-14 14:42:21 +08:00
|
|
|
/* Read Phy Status register twice to get the confirmation of the current
|
|
|
|
* link status.
|
|
|
|
*/
|
2021-05-14 14:22:23 +08:00
|
|
|
XEmacLite_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
|
|
|
|
XEmacLite_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
|
2021-05-13 16:33:40 +08:00
|
|
|
|
2021-05-14 14:22:23 +08:00
|
|
|
if (status & IEEE_STAT_AUTONEGOTIATE_COMPLETE)
|
2021-05-14 14:42:21 +08:00
|
|
|
return 1;
|
2021-05-14 14:22:23 +08:00
|
|
|
return 0;
|
2021-05-13 16:33:40 +08:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
void eth_link_detect(struct netif *netif)
|
|
|
|
{
|
2021-05-14 14:22:23 +08:00
|
|
|
u32_t link_speed, phy_link_status;
|
|
|
|
struct xemac_s *xemac = (struct xemac_s *)(netif->state);
|
2021-05-13 16:33:40 +08:00
|
|
|
|
|
|
|
#if defined(XLWIP_CONFIG_INCLUDE_GEM)
|
2021-05-14 14:22:23 +08:00
|
|
|
xemacpsif_s *xemacs = (xemacpsif_s *)(xemac->state);
|
|
|
|
XEmacPs *xemacp = &xemacs->emacps;
|
2021-05-13 16:33:40 +08:00
|
|
|
#elif defined(XLWIP_CONFIG_INCLUDE_AXI_ETHERNET)
|
2021-05-14 14:22:23 +08:00
|
|
|
xaxiemacif_s *xemacs = (xaxiemacif_s *)(xemac->state);
|
|
|
|
XAxiEthernet *xemacp = &xemacs->axi_ethernet;
|
2021-05-13 16:33:40 +08:00
|
|
|
#elif defined(XLWIP_CONFIG_INCLUDE_EMACLITE)
|
2021-05-14 14:22:23 +08:00
|
|
|
xemacliteif_s *xemacs = (xemacliteif_s *)(xemac->state);
|
|
|
|
XEmacLite *xemacp = xemacs->instance;
|
2021-05-13 16:33:40 +08:00
|
|
|
#endif
|
|
|
|
|
2021-05-14 14:22:23 +08:00
|
|
|
if ((xemacp->IsReady != (u32)XIL_COMPONENT_IS_READY) ||
|
2021-05-14 14:42:21 +08:00
|
|
|
(eth_link_status == ETH_LINK_UNDEFINED))
|
|
|
|
return;
|
2021-05-14 14:22:23 +08:00
|
|
|
|
|
|
|
phy_link_status = phy_link_detect(xemacp, phyaddrforemac);
|
|
|
|
|
|
|
|
if ((eth_link_status == ETH_LINK_UP) && (!phy_link_status))
|
2021-05-14 14:42:21 +08:00
|
|
|
eth_link_status = ETH_LINK_DOWN;
|
2021-05-14 14:22:23 +08:00
|
|
|
|
|
|
|
switch (eth_link_status) {
|
2021-05-14 14:42:21 +08:00
|
|
|
case ETH_LINK_UNDEFINED:
|
|
|
|
case ETH_LINK_UP:
|
|
|
|
return;
|
|
|
|
case ETH_LINK_DOWN:
|
|
|
|
netif_set_link_down(netif);
|
|
|
|
eth_link_status = ETH_LINK_NEGOTIATING;
|
|
|
|
xil_printf("Ethernet Link down\r\n");
|
|
|
|
break;
|
|
|
|
case ETH_LINK_NEGOTIATING:
|
|
|
|
if (phy_link_status &&
|
|
|
|
phy_autoneg_status(xemacp, phyaddrforemac)) {
|
|
|
|
|
|
|
|
/* Initiate Phy setup to get link speed */
|
2021-05-13 16:33:40 +08:00
|
|
|
#if defined(XLWIP_CONFIG_INCLUDE_GEM)
|
2021-05-14 14:42:21 +08:00
|
|
|
link_speed = phy_setup_emacps(xemacp,
|
|
|
|
phyaddrforemac);
|
|
|
|
XEmacPs_SetOperatingSpeed(xemacp, link_speed);
|
2021-05-13 16:33:40 +08:00
|
|
|
#elif defined(XLWIP_CONFIG_INCLUDE_AXI_ETHERNET)
|
2021-05-14 14:42:21 +08:00
|
|
|
link_speed = phy_setup_axiemac(xemacp);
|
|
|
|
XAxiEthernet_SetOperatingSpeed(xemacp,
|
|
|
|
link_speed);
|
2021-05-13 16:33:40 +08:00
|
|
|
#endif
|
2021-05-14 14:42:21 +08:00
|
|
|
netif_set_link_up(netif);
|
|
|
|
eth_link_status = ETH_LINK_UP;
|
|
|
|
xil_printf("Ethernet Link up\r\n");
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
2021-05-13 16:33:40 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef OS_IS_FREERTOS
|
|
|
|
void link_detect_thread(void *p)
|
|
|
|
{
|
2021-05-14 14:22:23 +08:00
|
|
|
struct netif *netif = (struct netif *) p;
|
2021-05-13 16:33:40 +08:00
|
|
|
|
2021-05-14 14:22:23 +08:00
|
|
|
while (1) {
|
2021-05-14 14:42:21 +08:00
|
|
|
/* Call eth_link_detect() every second to detect Ethernet link
|
|
|
|
* change.
|
|
|
|
*/
|
|
|
|
eth_link_detect(netif);
|
|
|
|
vTaskDelay(LINK_DETECT_THREAD_INTERVAL / portTICK_RATE_MS);
|
|
|
|
}
|
2021-05-13 16:33:40 +08:00
|
|
|
}
|
|
|
|
#endif
|