242 lines
6.4 KiB
C
242 lines
6.4 KiB
C
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/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2017-08-24 chinesebear first version
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* 2020-08-10 lizhirui porting to ls2k
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*/
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#ifndef SYNOP_GMAC_PLAT_H
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#define SYNOP_GMAC_PLAT_H 1
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/* sw
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#include <linux/kernel.h>
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#include <asm/io.h>
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#include <linux/gfp.h>
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#include <linux/slab.h>
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#include <linux/pci.h>
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*/
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#include "synopGMAC_types.h"
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#include "synopGMAC_debug.h"
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//#include "mii.h"
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//#include "GMAC_Pmon.h"
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//#include "synopGMAC_Host.h"
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#include <rtthread.h>
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#include <stdint.h>
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#include "mips_addrspace.h"
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//sw: copy the type define into here
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#define IOCTL_READ_REGISTER SIOCDEVPRIVATE+1
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#define IOCTL_WRITE_REGISTER SIOCDEVPRIVATE+2
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#define IOCTL_READ_IPSTRUCT SIOCDEVPRIVATE+3
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#define IOCTL_READ_RXDESC SIOCDEVPRIVATE+4
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#define IOCTL_READ_TXDESC SIOCDEVPRIVATE+5
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#define IOCTL_POWER_DOWN SIOCDEVPRIVATE+6
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#define SYNOP_GMAC0 1
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typedef int bool;
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//typedef unsigned long dma_addr_t;
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#define KUSEG_ADDR 0x0
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#define CACHED_MEMORY_ADDR KSEG0BASE
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#define UNCACHED_MEMORY_ADDR KSEG0BASE
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#define KSEG2_ADDR KSEG2BASE
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#define MAX_MEM_ADDR KSEG3BASE
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#define RESERVED_ADDR KSEG3BASE
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#define CACHED_TO_PHYS(x) ((uint64_t)(x) - CACHED_MEMORY_ADDR)
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#define PHYS_TO_CACHED(x) ((uint64_t)(x) + CACHED_MEMORY_ADDR)
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#define UNCACHED_TO_PHYS(x) ((uint64_t)(x) - UNCACHED_MEMORY_ADDR)
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#define PHYS_TO_UNCACHED(x) ((uint64_t)(x) + UNCACHED_MEMORY_ADDR)
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#define VA_TO_CINDEX(x) (PHYS_TO_CACHED(UNCACHED_TO_PHYS(x)))
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#define CACHED_TO_UNCACHED(x) (PHYS_TO_UNCACHED(CACHED_TO_PHYS(x)))
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#define VA_TO_PA(x) CACHED_TO_PHYS(x)
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/* sw
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#define TR0(fmt, args...) printk(KERN_CRIT "SynopGMAC: " fmt, ##args)
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#ifdef DEBUG
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#undef TR
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# define TR(fmt, args...) printk(KERN_CRIT "SynopGMAC: " fmt, ##args)
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#else
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# define TR(fmt, args...) // not debugging: nothing
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#endif
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*/
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/*
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#define TR0(fmt, args...) printf("SynopGMAC: " fmt, ##args)
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*/
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/*
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#ifdef DEBUG
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#undef TR
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# define TR(fmt, args...) printf("SynopGMAC: " fmt, ##args)
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#else
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//# define TR(fmt, args...) // not debugging: nothing
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#define TR(fmt, args...) printf("SynopGMAC: " fmt, ##args)
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#endif
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*/
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//sw: nothing to display
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#define TR0(fmt, args...) //rt_kprintf(fmt, ##args)
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#define TR(fmt, args...) //rt_kprintf(fmt, ##args)
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//typedef int bool;
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enum synopGMAC_boolean
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{
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false = 0,
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true = 1
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};
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#define DEFAULT_DELAY_VARIABLE 10
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#define DEFAULT_LOOP_VARIABLE 10000
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/* There are platform related endian conversions
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*
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*/
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#define LE32_TO_CPU __le32_to_cpu
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#define BE32_TO_CPU __be32_to_cpu
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#define CPU_TO_LE32 __cpu_to_le32
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/* Error Codes */
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#define ESYNOPGMACNOERR 0
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#define ESYNOPGMACNOMEM 1
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#define ESYNOPGMACPHYERR 2
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#define ESYNOPGMACBUSY 3
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struct Network_interface_data
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{
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u32 unit;
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u64 addr;
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u32 data;
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};
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/**
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* These are the wrapper function prototypes for OS/platform related routines
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*/
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void * plat_alloc_memory(u32 );
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void plat_free_memory(void *);
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//void * plat_alloc_consistent_dmaable_memory(struct pci_dev *, u32, u32 *);
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//void plat_free_consistent_dmaable_memory (struct pci_dev *, u32, void *, u32);
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void plat_delay(u32);
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/**
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* The Low level function to read register contents from Hardware.
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*
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* @param[in] pointer to the base of register map
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* @param[in] Offset from the base
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* \return Returns the register contents
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*/
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static u32 synopGMACReadReg(u64 RegBase, u32 RegOffset)
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{
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u64 addr;
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u32 data;
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addr = RegBase + (u32)RegOffset;
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data = *(volatile u32 *)addr;
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#if SYNOP_REG_DEBUG
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TR("%s RegBase = 0x%08x RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__, (u32)RegBase, RegOffset, data );
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#endif
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// rt_kprintf("%s RegBase = 0x%08x RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__, (u32)RegBase, RegOffset, data );
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return data;
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}
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/**
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* The Low level function to write to a register in Hardware.
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*
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* @param[in] pointer to the base of register map
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* @param[in] Offset from the base
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* @param[in] Data to be written
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* \return void
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*/
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static void synopGMACWriteReg(u64 RegBase, u32 RegOffset, u32 RegData )
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{
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u64 addr;
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addr = RegBase + (u32)RegOffset;
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// rt_kprintf("%s RegBase = 0x%08x RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__,(u32) RegBase, RegOffset, RegData );
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#if SYNOP_REG_DEBUG
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TR("%s RegBase = 0x%p RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__,(u32) RegBase, RegOffset, RegData );
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#endif
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*(volatile u32 *)addr = RegData;
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/*if(addr == 0xbfe1100c)
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DEBUG_MES("regdata = %08x\n", RegData);*/
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return;
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}
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/**
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* The Low level function to set bits of a register in Hardware.
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*
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* @param[in] pointer to the base of register map
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* @param[in] Offset from the base
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* @param[in] Bit mask to set bits to logical 1
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* \return void
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*/
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static void synopGMACSetBits(u64 RegBase, u32 RegOffset, u32 BitPos)
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{
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//u64 addr = (u64)RegBase + (u64)RegOffset;
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u32 data;
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data = synopGMACReadReg(RegBase, RegOffset);
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data |= BitPos;
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synopGMACWriteReg(RegBase, RegOffset, data);
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// writel(data,(void *)addr);
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#if SYNOP_REG_DEBUG
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TR("%s !!!!!!!!!!!!! RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__, RegOffset, data );
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#endif
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return;
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}
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/**
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* The Low level function to clear bits of a register in Hardware.
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*
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* @param[in] pointer to the base of register map
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* @param[in] Offset from the base
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* @param[in] Bit mask to clear bits to logical 0
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* \return void
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*/
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static void synopGMACClearBits(u64 RegBase, u32 RegOffset, u32 BitPos)
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{
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u32 data;
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data = synopGMACReadReg(RegBase, RegOffset);
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data &= (~BitPos);
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synopGMACWriteReg(RegBase, RegOffset, data);
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#if SYNOP_REG_DEBUG
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TR("%s !!!!!!!!!!!!! RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__, RegOffset, data );
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#endif
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return;
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}
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/**
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* The Low level function to Check the setting of the bits.
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*
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* @param[in] pointer to the base of register map
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* @param[in] Offset from the base
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* @param[in] Bit mask to set bits to logical 1
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* \return returns TRUE if set to '1' returns FALSE if set to '0'. Result undefined there are no bit set in the BitPos argument.
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*
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*/
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static bool synopGMACCheckBits(u64 RegBase, u32 RegOffset, u32 BitPos)
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{
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u32 data;
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data = synopGMACReadReg(RegBase, RegOffset);
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data &= BitPos;
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if(data)
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{
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return true;
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}
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else
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{
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return false;
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}
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}
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#endif
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