2015-07-09 07:38:07 +08:00
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/*
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2018-12-24 18:49:00 +08:00
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* Copyright (c) 2006-2018, RT-Thread Development Team
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2015-07-09 07:38:07 +08:00
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*
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2018-12-24 18:49:00 +08:00
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* SPDX-License-Identifier: Apache-2.0
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2015-07-09 07:38:07 +08:00
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*
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* Change Logs:
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2018-05-10 22:20:37 +08:00
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* Date Author Notes
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* 2018-05-08 zhuangwei the first version
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2015-07-09 07:38:07 +08:00
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*/
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2018-05-10 22:20:37 +08:00
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#ifndef __DRV_UART_H__
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#define __DRV_UART_H__
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2015-07-09 07:38:07 +08:00
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#include "ls1c.h"
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#define DEV_CLK 252000000 // 252MHz
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2018-05-11 10:15:32 +08:00
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#define UART_BAUDRATE 115200
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#define UART0_BASE 0xBFE40000
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//#define UART0_1_BASE 0xBFE41000
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#define UART1_BASE 0xBFE44000
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#define UART2_BASE 0xBFE48000
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#define UART3_BASE 0xBFE4C000
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#define UART4_BASE 0xBFE4C400
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#define UART5_BASE 0xBFE4C500
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#define UART6_BASE 0xBFE4C600
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#define UART7_BASE 0xBFE4C700
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#define UART8_BASE 0xBFE4C800
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#define UART9_BASE 0xBFE4C900
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#define UART10_BASE 0xBFE4Ca00
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#define UART11_BASE 0xBFE4Cb00
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2015-07-09 07:38:07 +08:00
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/* UART registers */
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2018-05-11 10:15:32 +08:00
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#define UART_DAT(base) __REG8(base + 0x00)
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#define UART_IER(base) __REG8(base + 0x01)
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#define UART_IIR(base) __REG8(base + 0x02)
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#define UART_FCR(base) __REG8(base + 0x02)
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#define UART_LCR(base) __REG8(base + 0x03)
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#define UART_MCR(base) __REG8(base + 0x04)
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#define UART_LSR(base) __REG8(base + 0x05)
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#define UART_MSR(base) __REG8(base + 0x06)
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#define UART_LSB(base) __REG8(base + 0x00)
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#define UART_MSB(base) __REG8(base + 0x01)
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2015-07-09 07:38:07 +08:00
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/* UART0 registers */
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2018-05-11 10:15:32 +08:00
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#define UART0_DAT __REG8(UART0_BASE + 0x00)
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#define UART0_IER __REG8(UART0_BASE + 0x01)
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#define UART0_IIR __REG8(UART0_BASE + 0x02)
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#define UART0_FCR __REG8(UART0_BASE + 0x02)
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#define UART0_LCR __REG8(UART0_BASE + 0x03)
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#define UART0_MCR __REG8(UART0_BASE + 0x04)
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#define UART0_LSR __REG8(UART0_BASE + 0x05)
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#define UART0_MSR __REG8(UART0_BASE + 0x06)
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#define UART0_LSB __REG8(UART0_BASE + 0x00)
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#define UART0_MSB __REG8(UART0_BASE + 0x01)
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2015-07-09 07:38:07 +08:00
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/* UART1 registers */
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2018-05-11 10:15:32 +08:00
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#define UART1_DAT __REG8(UART1_BASE + 0x00)
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#define UART1_IER __REG8(UART1_BASE + 0x01)
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#define UART1_IIR __REG8(UART1_BASE + 0x02)
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#define UART1_FCR __REG8(UART1_BASE + 0x02)
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#define UART1_LCR __REG8(UART1_BASE + 0x03)
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#define UART1_MCR __REG8(UART1_BASE + 0x04)
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#define UART1_LSR __REG8(UART1_BASE + 0x05)
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#define UART1_MSR __REG8(UART1_BASE + 0x06)
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#define UART1_LSB __REG8(UART1_BASE + 0x00)
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#define UART1_MSB __REG8(UART1_BASE + 0x01)
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2015-07-09 07:38:07 +08:00
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/* UART interrupt enable register value */
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2018-05-11 10:15:32 +08:00
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#define UARTIER_IME (1 << 3)
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#define UARTIER_ILE (1 << 2)
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#define UARTIER_ITXE (1 << 1)
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#define UARTIER_IRXE (1 << 0)
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2015-07-09 07:38:07 +08:00
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/* UART line control register value */
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2018-05-11 10:15:32 +08:00
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#define UARTLCR_DLAB (1 << 7)
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#define UARTLCR_BCB (1 << 6)
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#define UARTLCR_SPB (1 << 5)
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#define UARTLCR_EPS (1 << 4)
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#define UARTLCR_PE (1 << 3)
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#define UARTLCR_SB (1 << 2)
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2015-07-09 07:38:07 +08:00
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/* UART line status register value */
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2018-05-11 10:15:32 +08:00
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#define UARTLSR_ERROR (1 << 7)
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#define UARTLSR_TE (1 << 6)
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#define UARTLSR_TFE (1 << 5)
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#define UARTLSR_BI (1 << 4)
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#define UARTLSR_FE (1 << 3)
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#define UARTLSR_PE (1 << 2)
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#define UARTLSR_OE (1 << 1)
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#define UARTLSR_DR (1 << 0)
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2015-07-09 07:38:07 +08:00
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void rt_hw_uart_init(void);
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2018-05-10 22:20:37 +08:00
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2015-07-09 07:38:07 +08:00
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#endif
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