529 lines
14 KiB
C
529 lines
14 KiB
C
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/*
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* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/******************************************************************************
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* @file dw_gpio.c
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* @brief CSI Source File for GPIO Driver
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* @version V1.0
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* @date 02. June 2017
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******************************************************************************/
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#include <stdbool.h>
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#include <stdio.h>
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#include "csi_core.h"
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#include "drv_gpio.h"
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#include "dw_gpio.h"
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#define ERR_GPIO(errno) (CSI_DRV_ERRNO_GPIO_BASE | errno)
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#define GPIO_NULL_PARAM_CHK(para) \
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do { \
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if (para == NULL) { \
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return ERR_GPIO(EDRV_PARAMETER); \
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} \
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} while (0)
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typedef struct {
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uint32_t base; ///< handle register base
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uint32_t irq; ///< irq of this handle
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uint32_t pin_num; ///< pin number of this handle
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uint32_t cb; ///< callback function
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gpio_mode_e mode; ///< gpio mode
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gpio_direction_e dir; ///< gpio direction
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uint32_t mask; ///< gpio mask bit
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uint32_t value; ///< gpio value
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} dw_gpio_priv_t;
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typedef struct {
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gpio_port_handle_t handle;
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uint8_t idx;
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pin_t pin_name;
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} dw_gpio_pin_priv_t;
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static dw_gpio_priv_t gpio_handle[CONFIG_GPIO_NUM];
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static dw_gpio_pin_priv_t gpio_pin_handle[CONFIG_GPIO_PIN_NUM];
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/* Driver Capabilities */
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static const gpio_capabilities_t driver_capabilities = {
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.interrupt_mode = 1, /* intrrupt mode */
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.pull_mode = 1 /* pull mode */
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};
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//
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// Functions
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//
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static dw_gpio_reg_t *gpio_reg = NULL;
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static dw_gpio_control_reg_t *gpio_control_reg = NULL;
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static int32_t gpio_set_direction(
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void *port,
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gpio_direction_e direction
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)
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{
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dw_gpio_priv_t *gpio_priv = port;
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if (direction == GPIO_DIRECTION_INPUT) {
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gpio_reg->SWPORT_DDR &= (~gpio_priv->mask);
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} else if (direction == GPIO_DIRECTION_OUTPUT) {
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gpio_reg->SWPORT_DDR |= gpio_priv->mask;
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} else {
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return ERR_GPIO(EDRV_PARAMETER);
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}
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return 0;
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}
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/*
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* Read the statu of the Port choosed.
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* Parameters:
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* port: use to choose a I/O port among Port A, B, or C.
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* return: the value of the corresponding Port.
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*/
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int32_t gpio_read(uint32_t *value)
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{
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*value = gpio_control_reg->EXT_PORTA;
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return 0;
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}
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/*
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* Write an output value to corresponding Port.
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* Parameters:
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* port: use to choose a I/O port among Port A, B, or C.
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* output: value that will be written to the corresponding Port.
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* return: SUCCESS
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*/
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static int32_t gpio_write(void *port, uint32_t mask)
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{
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dw_gpio_priv_t *gpio_priv = port;
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uint32_t value = gpio_reg->SWPORT_DR;
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value &= ~(mask);
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value |= gpio_priv->value;
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gpio_reg->SWPORT_DR = value;
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return 0;
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}
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/**
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* Configure a GPIO gpio_set_irq_mode.
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* @param[in] pin the addr store the pin num.
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* @param[in] _irqmode the irqmode of gpio
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* @return zero on success. -1 on falure.
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*/
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static int32_t gpio_set_irq_mode(gpio_pin_handle_t pin, gpio_irq_mode_e irq_mode)
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{
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dw_gpio_pin_priv_t *gpio_pin_priv = pin;
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uint32_t offset = gpio_pin_priv->idx;
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uint32_t mask = 1 << offset;
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switch (irq_mode) {
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/* rising edge interrupt mode */
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case GPIO_IRQ_MODE_RISING_EDGE:
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gpio_control_reg->INTTYPE_LEVEL |= mask;
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gpio_control_reg->INT_POLARITY |= mask;
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break;
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/* falling edge interrupt mode */
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case GPIO_IRQ_MODE_FALLING_EDGE:
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gpio_control_reg->INTTYPE_LEVEL |= mask;
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gpio_control_reg->INT_POLARITY &= (~mask);
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break;
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/* low level interrupt mode */
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case GPIO_IRQ_MODE_LOW_LEVEL:
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gpio_control_reg->INTTYPE_LEVEL &= (~mask);
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gpio_control_reg->INT_POLARITY &= (~mask);
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break;
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/* high level interrupt mode */
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case GPIO_IRQ_MODE_HIGH_LEVEL:
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gpio_control_reg->INTTYPE_LEVEL &= (~mask);
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gpio_control_reg->INT_POLARITY |= mask;
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break;
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/* double edge interrupt mode */
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case GPIO_IRQ_MODE_DOUBLE_EDGE:
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return ERR_GPIO(EDRV_UNSUPPORTED);
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default:
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return ERR_GPIO(EDRV_PARAMETER);
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}
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return 0;
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}
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/*
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* Clear one or more interrupts of PortA.
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* Parameters:
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* pinno:
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* return: SUCCESS.
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*/
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static void gpio_irq_clear(uint32_t idx)
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{
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gpio_control_reg->PORTA_EOI = idx;
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}
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/*
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* Enable one or more interrupts of PortA.
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* Parameters:
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* pinno:
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* return: SUCCESS.
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*/
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static void gpio_irq_enable(gpio_pin_handle_t pin)
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{
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dw_gpio_pin_priv_t *gpio_pin_priv = pin;
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uint32_t offset = gpio_pin_priv->idx;
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uint32_t val = gpio_control_reg->INTEN;
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val |= (1 << offset);
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gpio_control_reg->INTEN = val;
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}
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/*
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* Disable one or more interrupts of PortA.
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* Parameters:
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* pinno:
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* return: SUCCESS.
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*/
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static void gpio_irq_disable(gpio_pin_handle_t pin)
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{
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dw_gpio_pin_priv_t *gpio_pin_priv = pin;
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uint32_t offset = gpio_pin_priv->idx;
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uint32_t val = gpio_control_reg->INTEN;
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val &= ~(1 << offset);
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gpio_control_reg->INTEN = val;
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}
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void dw_gpio_irqhandler(int idx)
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{
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dw_gpio_priv_t *gpio_priv = &gpio_handle[idx];
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uint32_t value = gpio_control_reg->INTSTATUS;
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uint8_t i;
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/* find the interrput pin */
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for (i = 0; i < 32; i++) {
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if (value == (1 << i)) {
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break;
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}
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}
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uint32_t offset = i;
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uint32_t pin_idx = offset;
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for (i = 0; i < idx; i++) {
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pin_idx += gpio_handle[i].pin_num;
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}
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gpio_pin_handle_t pin = (gpio_pin_handle_t) &gpio_pin_handle[pin_idx];
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/* execute the callback function */
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if ((gpio_event_cb_t)(gpio_priv->cb)) {
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((gpio_event_cb_t)(gpio_priv->cb))(pin);
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}
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gpio_irq_clear(value); //clear the gpio interrupt
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}
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int32_t __attribute__((weak)) target_gpio_port_init(port_name_t port, uint32_t *base, uint32_t *irq, uint32_t *pin_num)
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{
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return -1;
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}
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/**
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\brief Initialize GPIO module. 1. Initializes the resources needed for the GPIO handle 2.registers event callback function
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3.get gpio_port_handle
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\param[in] port port_name.
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\param[in] cb_event Pointer to \ref gpio_event_cb_t
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\return gpio_port_handle
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*/
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gpio_port_handle_t csi_gpio_port_initialize(port_name_t port, gpio_event_cb_t cb_event)
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{
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uint32_t i;
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dw_gpio_priv_t *gpio_priv;
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for (i = 0; i <= port; i++) {
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/* obtain the gpio port information */
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uint32_t base = 0u;
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uint32_t pin_num;
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uint32_t irq;
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uint32_t idx = target_gpio_port_init(i, &base, &irq, &pin_num);
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if (idx < 0 || idx >= CONFIG_GPIO_NUM) {
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return NULL;
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}
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gpio_priv = &gpio_handle[idx];
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gpio_priv->base = base;
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gpio_priv->irq = irq;
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gpio_priv->pin_num = pin_num;
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}
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gpio_reg = (dw_gpio_reg_t *)(gpio_priv->base);
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gpio_control_reg = (dw_gpio_control_reg_t *)(gpio_priv->base + 0x30);
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gpio_priv->cb = (uint32_t)cb_event;
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drv_nvic_enable_irq(gpio_priv->irq);
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return (gpio_port_handle_t)gpio_priv;
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}
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/**
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\brief De-initialize GPIO handle. stops operation and releases the software resources used by the handle
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\param[in] handle gpio port handle to operate.
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\return error code
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*/
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int32_t csi_gpio_port_uninitialize(gpio_port_handle_t handle)
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{
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GPIO_NULL_PARAM_CHK(handle);
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dw_gpio_priv_t *gpio_priv = handle;
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gpio_priv->cb = NULL;
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drv_nvic_disable_irq(gpio_priv->irq);
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return 0;
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}
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/**
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\brief Get driver capabilities.
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\param[in] handle instance to operate.
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\return \ref gpio_capabilities_t
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*/
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gpio_capabilities_t csi_gpio_get_io_capabilities(gpio_port_handle_t handle)
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{
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return driver_capabilities;
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}
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/**
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\brief config multiple pin within one handle
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\param[in] handle gpio port handle to operate.
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\param[in] mask the bitmask to identify which bits in the handle should be included (0 - ignore)
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\param[in] mode \ref gpio_mode_e
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\param[in] dir \ref gpio_direction_e
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\return error code
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*/
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int32_t csi_gpio_port_config(gpio_port_handle_t handle, uint32_t mask, gpio_mode_e mode, gpio_direction_e dir)
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{
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if (mask < 0) {
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return ERR_GPIO(EDRV_PARAMETER);
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}
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GPIO_NULL_PARAM_CHK(handle);
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dw_gpio_priv_t *gpio_priv = handle;
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/*config the gpio mode direction mask bits */
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gpio_priv->mode = mode;
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gpio_priv->dir = dir;
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gpio_priv->mask = mask;
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uint32_t ret = gpio_set_direction(gpio_priv, dir);
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return ret;
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}
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/**
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\brief Write value to the handle(write value to multiple pins on one handle at the same time)
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\param[in] handle gpio port handle to operate.
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\param[in] mask The bitmask to identify which bits in the handle should be included (0 - ignore)
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\param[in] value the value to be set
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\return error code
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*/
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int32_t csi_gpio_port_write(gpio_port_handle_t handle, uint32_t mask, uint32_t value)
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{
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if (mask < 0 || value < 0) {
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return ERR_GPIO(EDRV_PARAMETER);
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}
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GPIO_NULL_PARAM_CHK(handle);
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uint32_t port_value = mask & value;
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dw_gpio_priv_t *gpio_priv = handle;
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gpio_priv->value = port_value;
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gpio_write(gpio_priv, mask);
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return 0;
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}
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/**
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\brief Read the current value on the handle(read value of multiple pins on one handle at the same time)
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\param[in] handle gpio port handle to operate.
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\param[in] mask The bitmask to identify which bits in the handle should be included (0 - ignore)
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\param[out] value an integer with each bit corresponding to an associated handle pin setting
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\return error code
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*/
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int32_t csi_gpio_port_read(gpio_port_handle_t handle, uint32_t mask, uint32_t *value)
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{
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if (mask < 0) {
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return ERR_GPIO(EDRV_PARAMETER);
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}
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GPIO_NULL_PARAM_CHK(handle);
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GPIO_NULL_PARAM_CHK(value);
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uint32_t port_value = 0;
|
||
|
|
|
||
|
|
gpio_read(&port_value);
|
||
|
|
*value = (mask & port_value);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
int32_t __attribute__((weak)) target_gpio_pin_init(pin_t gpio_pin, uint32_t *port_idx)
|
||
|
|
{
|
||
|
|
return -1;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
\brief Initialize GPIO handle.
|
||
|
|
\param[in] gpio_pin Pointer to the pin_t.
|
||
|
|
\return gpio_pin_handle
|
||
|
|
*/
|
||
|
|
gpio_pin_handle_t csi_gpio_pin_initialize(pin_t gpio_pin)
|
||
|
|
{
|
||
|
|
/* obtain the gpio pin information */
|
||
|
|
uint32_t port_idx;
|
||
|
|
uint32_t pin_idx = target_gpio_pin_init(gpio_pin, &port_idx);
|
||
|
|
|
||
|
|
dw_gpio_pin_priv_t *gpio_pin_priv = &(gpio_pin_handle[pin_idx]);
|
||
|
|
gpio_pin_priv->handle = (gpio_port_handle_t)&gpio_handle[port_idx];
|
||
|
|
|
||
|
|
uint32_t idx = pin_idx;
|
||
|
|
uint32_t i;
|
||
|
|
|
||
|
|
for (i = 0; i < port_idx; i++) {
|
||
|
|
idx = pin_idx - (gpio_handle[i].pin_num);
|
||
|
|
}
|
||
|
|
|
||
|
|
gpio_pin_priv->idx = idx;
|
||
|
|
|
||
|
|
return (gpio_pin_handle_t)gpio_pin_priv;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
\brief config pin
|
||
|
|
\param[in] pin gpio pin handle to operate.
|
||
|
|
\param[in] mode \ref gpio_mode_e
|
||
|
|
\param[in] dir \ref gpio_direction_e
|
||
|
|
\return error code
|
||
|
|
*/
|
||
|
|
int32_t csi_gpio_pin_config(gpio_pin_handle_t pin,
|
||
|
|
gpio_mode_e mode,
|
||
|
|
gpio_direction_e dir)
|
||
|
|
{
|
||
|
|
GPIO_NULL_PARAM_CHK(pin);
|
||
|
|
|
||
|
|
/* config the gpio pin mode direction mask bits */
|
||
|
|
dw_gpio_pin_priv_t *gpio_pin_priv = pin;
|
||
|
|
dw_gpio_priv_t *gpio_priv = gpio_pin_priv->handle;
|
||
|
|
|
||
|
|
gpio_priv->mode = mode;
|
||
|
|
gpio_priv->dir = dir;
|
||
|
|
gpio_priv->mask = 1 << gpio_pin_priv->idx;
|
||
|
|
|
||
|
|
uint32_t ret = gpio_set_direction(gpio_priv, dir);
|
||
|
|
if(ret) {
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
\brief Set one or zero to the selected GPIO pin.
|
||
|
|
\param[in] pin gpio pin handle to operate.
|
||
|
|
\param[in] value the value to be set
|
||
|
|
\return error code
|
||
|
|
*/
|
||
|
|
int32_t csi_gpio_pin_write(gpio_pin_handle_t pin, bool value)
|
||
|
|
{
|
||
|
|
GPIO_NULL_PARAM_CHK(pin);
|
||
|
|
if (value < 0) {
|
||
|
|
return ERR_GPIO(EDRV_PARAMETER);
|
||
|
|
}
|
||
|
|
|
||
|
|
dw_gpio_pin_priv_t *gpio_pin_priv = pin;
|
||
|
|
dw_gpio_priv_t *gpio_priv = gpio_pin_priv->handle;
|
||
|
|
uint8_t offset = gpio_pin_priv->idx;
|
||
|
|
uint32_t port_value = value << offset;
|
||
|
|
|
||
|
|
gpio_priv->value = port_value;
|
||
|
|
gpio_write(gpio_priv, (1 << offset));
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
\brief Get the value of selected GPIO pin.
|
||
|
|
\param[in] pin gpio pin handle to operate.
|
||
|
|
\param[out] value buf to store the pin value
|
||
|
|
\return error code
|
||
|
|
*/
|
||
|
|
int32_t csi_gpio_pin_read(gpio_pin_handle_t pin, bool *value)
|
||
|
|
{
|
||
|
|
GPIO_NULL_PARAM_CHK(pin);
|
||
|
|
if (value <= 0) {
|
||
|
|
return ERR_GPIO(EDRV_PARAMETER);
|
||
|
|
}
|
||
|
|
|
||
|
|
dw_gpio_pin_priv_t *gpio_pin_priv = pin;
|
||
|
|
uint32_t port_value;
|
||
|
|
uint8_t offset = gpio_pin_priv->idx;
|
||
|
|
|
||
|
|
gpio_read(&port_value);
|
||
|
|
*value = (port_value & (1 << offset)) >> offset;
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
\brief set GPIO interrupt mode.
|
||
|
|
\param[in] pin gpio pin handle to operate.
|
||
|
|
\param[in] mode the irq mode to be set
|
||
|
|
\param[in] enable the enable flag
|
||
|
|
\return error code
|
||
|
|
*/
|
||
|
|
int32_t csi_gpio_pin_irq_set(gpio_pin_handle_t pin, gpio_irq_mode_e mode, bool enable)
|
||
|
|
{
|
||
|
|
GPIO_NULL_PARAM_CHK(pin);
|
||
|
|
|
||
|
|
uint32_t ret = 0;
|
||
|
|
|
||
|
|
if (enable) {
|
||
|
|
ret = gpio_set_irq_mode(pin, mode);
|
||
|
|
|
||
|
|
if (ret) {
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
gpio_irq_enable(pin);
|
||
|
|
|
||
|
|
} else {
|
||
|
|
gpio_irq_disable(pin);
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
|
||
|
|
}
|
||
|
|
|