2015-11-11 23:44:05 +08:00
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/*
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2018-10-15 01:35:07 +08:00
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* Copyright (c) 2006-2018, RT-Thread Development Team
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2015-11-11 23:44:05 +08:00
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*
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2018-10-15 01:35:07 +08:00
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* SPDX-License-Identifier: Apache-2.0
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2015-11-11 23:44:05 +08:00
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*
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* Change Logs:
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* Date Author Notes
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* 2015-04-06 zchong the first version
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*/
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MODULE ?cstartup
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; --------------------
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; Mode, correspords to bits 0-5 in CPSR
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MODE_MSK DEFINE 0x1F ; Bit mask for mode bits in CPSR
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I_Bit DEFINE 0x80 ; when I bit is set, IRQ is disabled
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F_Bit DEFINE 0x40 ; when F bit is set, FIQ is disabled
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USR_MODE DEFINE 0x10 ; User mode
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FIQ_MODE DEFINE 0x11 ; Fast Interrupt Request mode
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IRQ_MODE DEFINE 0x12 ; Interrupt Request mode
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SVC_MODE DEFINE 0x13 ; Supervisor mode
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ABT_MODE DEFINE 0x17 ; Abort mode
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UND_MODE DEFINE 0x1B ; Undefined Instruction mode
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SYS_MODE DEFINE 0x1F ; System mode
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;; Forward declaration of sections.
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SECTION IRQ_STACK:DATA:NOROOT(3)
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SECTION FIQ_STACK:DATA:NOROOT(3)
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SECTION SVC_STACK:DATA:NOROOT(3)
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SECTION ABT_STACK:DATA:NOROOT(3)
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SECTION UND_STACK:DATA:NOROOT(3)
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SECTION CSTACK:DATA:NOROOT(3)
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SECTION .text:CODE
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SECTION .intvec:CODE:NOROOT(5)
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PUBLIC __vector
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PUBLIC __iar_program_start
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__iar_init$$done: ; The vector table is not needed
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; until after copy initialization is done
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__vector: ; Make this a DATA label, so that stack usage
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; analysis doesn't consider it an uncalled fun
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ARM
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; All default exception handlers (except reset) are
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; defined as weak symbol definitions.
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; If a handler is defined by the application it will take precedence.
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LDR PC,Reset_Addr ; Reset
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LDR PC,Undefined_Addr ; Undefined instructions
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LDR PC,SWI_Addr ; Software interrupt (SWI/SVC)
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LDR PC,Prefetch_Addr ; Prefetch abort
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LDR PC,Abort_Addr ; Data abort
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DCD 0 ; RESERVED
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LDR PC,IRQ_Addr ; IRQ
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LDR PC,FIQ_Addr ; FIQ
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DATA
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Reset_Addr: DCD __iar_program_start
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Undefined_Addr: DCD Undefined_Handler
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SWI_Addr: DCD SWI_Handler
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Prefetch_Addr: DCD Prefetch_Handler
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Abort_Addr: DCD Abort_Handler
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IRQ_Addr: DCD IRQ_Handler
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FIQ_Addr: DCD FIQ_Handler
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; --------------------------------------------------
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; ?cstartup -- low-level system initialization code.
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;
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; After a reset execution starts here, the mode is ARM, supervisor
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; with interrupts disabled.
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;
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SECTION .text:CODE:NOROOT(2)
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EXTERN rt_hw_trap_udef
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EXTERN rt_hw_trap_swi
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EXTERN rt_hw_trap_pabt
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EXTERN rt_hw_trap_dabt
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EXTERN rt_hw_trap_fiq
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EXTERN rt_hw_trap_irq
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EXTERN rt_interrupt_enter
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EXTERN rt_interrupt_leave
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EXTERN rt_thread_switch_interrupt_flag
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EXTERN rt_interrupt_from_thread
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EXTERN rt_interrupt_to_thread
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EXTERN rt_current_thread
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EXTERN vmm_thread
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EXTERN vmm_virq_check
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EXTERN __cmain
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REQUIRE __vector
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EXTWEAK __iar_init_core
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EXTWEAK __iar_init_vfp
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ARM
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__iar_program_start:
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?cstartup:
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;
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; Add initialization needed before setup of stackpointers here.
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;
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;
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; Initialize the stack pointers.
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; The pattern below can be used for any of the exception stacks:
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; FIQ, IRQ, SVC, ABT, UND, SYS.
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; The USR mode uses the same stack as SYS.
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; The stack segments must be defined in the linker command file,
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; and be declared above.
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;
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MRS r0, cpsr ; Original PSR value
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;; Set up the interrupt stack pointer.
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BIC r0, r0, #MODE_MSK ; Clear the mode bits
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ORR r0, r0, #IRQ_MODE ; Set IRQ mode bits
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MSR cpsr_c, r0 ; Change the mode
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LDR sp, =SFE(IRQ_STACK) ; End of IRQ_STACK
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BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
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;; Set up the fast interrupt stack pointer.
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BIC r0, r0, #MODE_MSK ; Clear the mode bits
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ORR r0, r0, #FIQ_MODE ; Set FIR mode bits
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MSR cpsr_c, r0 ; Change the mode
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LDR sp, =SFE(FIQ_STACK) ; End of FIQ_STACK
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BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
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BIC r0,r0,#MODE_MSK ; Clear the mode bits
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ORR r0,r0,#ABT_MODE ; Set Abort mode bits
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MSR cpsr_c,r0 ; Change the mode
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LDR sp,=SFE(ABT_STACK) ; End of ABT_STACK
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BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
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BIC r0,r0,#MODE_MSK ; Clear the mode bits
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ORR r0,r0,#UND_MODE ; Set Undefined mode bits
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MSR cpsr_c,r0 ; Change the mode
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LDR sp,=SFE(UND_STACK) ; End of UND_STACK
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BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
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;; Set up the normal stack pointer.
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BIC r0 ,r0, #MODE_MSK ; Clear the mode bits
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ORR r0 ,r0, #SVC_MODE ; Set System mode bits
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MSR cpsr_c, r0 ; Change the mode
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LDR sp, =SFE(SVC_STACK) ; End of SVC_STACK
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BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
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;; Turn on core features assumed to be enabled.
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BL __iar_init_core
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;; Initialize VFP (if needed).
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BL __iar_init_vfp
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;; Continue to __cmain for C-level initialization.
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B __cmain
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Undefined_Handler:
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SUB sp, sp, #72
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STMIA sp, {r0 - r12} ;/* Calling r0-r12 */
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ADD r8, sp, #60
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MRS r1, cpsr
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MRS r2, spsr
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ORR r2,r2, #I_Bit | F_Bit
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MSR cpsr_c, r2
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MOV r0, r0
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STMDB r8, {sp, lr} ;/* Calling SP, LR */
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MSR cpsr_c, r1 ;/* return to Undefined Instruction mode */
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STR lr, [r8, #0] ;/* Save calling PC */
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MRS r6, spsr
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STR r6, [r8, #4] ;/* Save CPSR */
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STR r0, [r8, #8] ;/* Save OLD_R0 */
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MOV r0, sp
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BL rt_hw_trap_udef
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LDMIA sp, {r0 - r12} ;/* Calling r0 - r2 */
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MOV r0, r0
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LDR lr, [sp, #60] ;/* Get PC */
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ADD sp, sp, #72
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MOVS pc, lr ;/* return & move spsr_svc into cpsr */
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SWI_Handler:
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BL rt_hw_trap_swi
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Prefetch_Handler:
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BL rt_hw_trap_pabt
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Abort_Handler:
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SUB sp, sp, #72
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STMIA sp, {r0 - r12} ;/* Calling r0-r12 */
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ADD r8, sp, #60
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STMDB r8, {sp, lr} ;/* Calling SP, LR */
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STR lr, [r8, #0] ;/* Save calling PC */
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MRS r6, spsr
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STR r6, [r8, #4] ;/* Save CPSR */
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STR r0, [r8, #8] ;/* Save OLD_R0 */
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MOV r0, sp
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BL rt_hw_trap_dabt
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LDMIA sp, {r0 - r12} ;/* Calling r0 - r2 */
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MOV r0, r0
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LDR lr, [sp, #60] ;/* Get PC */
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ADD sp, sp, #72
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MOVS pc, lr ;/* return & move spsr_svc into cpsr */
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FIQ_Handler:
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STMFD sp!,{r0-r7,lr}
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BL rt_hw_trap_fiq
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LDMFD sp!,{r0-r7,lr}
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SUBS pc,lr,#4
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IRQ_Handler:
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STMFD sp!, {r0-r12,lr}
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BL rt_interrupt_enter
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BL rt_hw_trap_irq
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BL rt_interrupt_leave
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; if rt_thread_switch_interrupt_flag set, jump to
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; rt_hw_context_switch_interrupt_do and don't return
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LDR r0, =rt_thread_switch_interrupt_flag
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LDR r1, [r0]
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CMP r1, #1
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BEQ rt_hw_context_switch_interrupt_do
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LDMFD sp!, {r0-r12,lr}
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SUBS pc, lr, #4
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rt_hw_context_switch_interrupt_do:
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MOV r1, #0 ; clear flag
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STR r1, [r0]
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LDMFD sp!, {r0-r12,lr}; reload saved registers
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STMFD sp, {r0-r2} ; save r0-r2
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MRS r0, spsr ; get cpsr of interrupt thread
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SUB r1, sp, #4*3
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SUB r2, lr, #4 ; save old task's pc to r2
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; switch to SVC mode with no interrupt
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MSR cpsr_c, #I_Bit | F_Bit | SVC_MODE
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STMFD sp!, {r2} ; push old task's pc
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STMFD sp!, {r3-r12,lr}; push old task's lr,r12-r4
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LDMFD r1, {r1-r3} ; restore r0-r2 of the interrupt thread
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STMFD sp!, {r1-r3} ; push old task's r0-r2
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STMFD sp!, {r0} ; push old task's cpsr
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LDR r4, =rt_interrupt_from_thread
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LDR r5, [r4]
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STR sp, [r5] ; store sp in preempted tasks's TCB
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LDR r6, =rt_interrupt_to_thread
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LDR r6, [r6]
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LDR sp, [r6] ; get new task's stack pointer
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LDMFD sp!, {r4} ; pop new task's cpsr to spsr
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MSR spsr_cxsf, r4
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LDMFD sp!, {r0-r12,lr,pc}^ ; pop new task's r0-r12,lr & pc, copy spsr to cpsr
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END
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