330 lines
8.7 KiB
C
330 lines
8.7 KiB
C
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/**
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*
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* \file
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*
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* \brief SAM Advanced Encryption Standard driver.
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*
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* This file defines a useful set of functions for the AES on SAM devices.
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*
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* Copyright (c) 2014-2016 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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*/
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/*
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* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
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*/
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#include <aes.h>
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#include <system.h>
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/**
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* \brief Initializes an AES configuration structure to defaults.
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*
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* Initializes the specified AES configuration structure to a set of
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* known default values.
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*
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* \note This function should be called to initialize <b>all</b> new instances of
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* AES configuration structures before they are further modified by the user
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* application.
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*
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* The default configuration is as follows:
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* - Data encryption
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* - 128-bit AES key size
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* - 128-bit cipher feedback size
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* - Manual start mode
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* - Electronic Codebook (ECB) mode
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* - All countermeasures are enabled
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* - XRO key is disabled
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* - Key generation is disabled
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* - Last output data mode is disabled
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*
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* \param[out] config Pointer to an AES configuration structure
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*/
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void aes_get_config_defaults(
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struct aes_config *const config)
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{
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/* Sanity check arguments */
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Assert(config);
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config->encrypt_mode = AES_ENCRYPTION;
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config->key_size = AES_KEY_SIZE_128;
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config->start_mode = AES_MANUAL_START;
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config->opmode= AES_ECB_MODE;
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config->cfb_size = AES_CFB_SIZE_128;
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config->ctype = AES_COUNTERMEASURE_TYPE_ALL;
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config->enable_xor_key = false;
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config->enable_key_gen = false;
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config->lod = false;
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}
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/**
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* \brief Initialize the AES module.
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*
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* \param[out] module Pointer to the software instance struct
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* \param[in] hw Module hardware register base address pointer
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* \param[in] config Pointer to an AES configuration structure
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*/
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void aes_init(
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struct aes_module *const module,
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Aes *const hw,
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struct aes_config *const config)
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{
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/* Sanity check arguments */
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Assert(hw);
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Assert(config);
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Assert(module);
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/* Enable clock for AES */
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system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_AES);
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/* Perform a software reset */
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hw->CTRLA.reg = AES_CTRLA_SWRST;
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/* Initialize the AES with new configurations */
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aes_set_config(module,hw, config);
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}
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/**
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* \brief Enable the AES module.
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*
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* \param[in,out] module Pointer to the software instance struct
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*/
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void aes_enable(struct aes_module *const module)
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{
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Assert(module);
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Assert(module->hw);
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module->hw->CTRLA.reg |= AES_CTRLA_ENABLE;
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}
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/**
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* \brief Disable the AES module.
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* \param[in] module Pointer to the software instance struct
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*/
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void aes_disable(struct aes_module *const module)
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{
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Assert(module);
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Assert(module->hw);
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/* Disbale interrupt */
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module->hw->INTENCLR.reg = AES_INTENCLR_MASK;
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/* Clear interrupt flag */
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module->hw->INTFLAG.reg = AES_INTFLAG_MASK;
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module->hw->CTRLA.reg &= (~AES_CTRLA_ENABLE);
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}
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/**
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* \brief Configure the AES module.
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*
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* \param[out] module Pointer to the software instance struct
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* \param[in] hw Module hardware register base address pointer
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* \param[in] config Pointer to an AES configuration structure
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*/
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void aes_set_config(
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struct aes_module *const module,
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Aes *const hw,
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struct aes_config *const config)
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{
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uint32_t ul_mode = 0;
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/* Validate arguments. */
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Assert(hw);
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Assert(config);
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Assert(module);
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module->opmode = config->opmode;
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module->hw = hw;
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module->key_size = config->key_size;
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module->cfb_size = config->cfb_size;
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ul_mode |= (config->encrypt_mode << AES_CTRLA_CIPHER_Pos)
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| (config->start_mode << AES_CTRLA_STARTMODE_Pos)
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| (config->key_size << AES_CTRLA_KEYSIZE_Pos)
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| (config->opmode << AES_CTRLA_AESMODE_Pos)
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| (config->cfb_size << AES_CTRLA_CFBS_Pos)
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| (AES_CTRLA_CTYPE(config->ctype))
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| (config->enable_xor_key << AES_CTRLA_XORKEY_Pos)
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| (config->enable_key_gen << AES_CTRLA_KEYGEN_Pos)
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| (config->lod << AES_CTRLA_LOD_Pos);
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if (hw->CTRLA.reg & AES_CTRLA_ENABLE) {
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aes_disable(module);
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hw->CTRLA.reg = ul_mode;
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aes_enable(module);
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} else {
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hw->CTRLA.reg = ul_mode;
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}
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}
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/**
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* \brief Write the 128/192/256-bit cryptographic key.
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*
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* \param[in] module Pointer to the software instance struct
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* \param[in] key Pointer to 4/6/8 contiguous 32-bit words
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*
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* \note The key size depends on the current AES configuration.
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*/
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void aes_write_key(
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struct aes_module *const module,
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const uint32_t *key)
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{
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uint32_t i, key_length = 0;
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/* Validate arguments. */
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Assert(module);
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Assert(module->hw);
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Assert(key);
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switch (module->key_size) {
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case AES_KEY_SIZE_128:
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key_length = 4;
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break;
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case AES_KEY_SIZE_192:
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key_length = 6;
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break;
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case AES_KEY_SIZE_256:
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key_length = 8;
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break;
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default:
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break;
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}
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for (i = 0; i < key_length; i++) {
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module->hw->KEYWORD[i].reg = *key;
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key++;
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}
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}
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/**
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* \brief Write the initialization vector (for the CBC, CFB, OFB, CTR, and GCM
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* cipher modes).
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*
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* \param[in] module Pointer to the software instance struct
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* \param[in] vector Pointer to four contiguous 32-bit words
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*/
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void aes_write_init_vector(
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struct aes_module *const module,
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const uint32_t *vector)
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{
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uint32_t i;
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/* Validate arguments. */
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Assert(module);
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Assert(module->hw);
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Assert(module->opmode != AES_ECB_MODE);
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for (i = 0; i < 4; i++) {
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module->hw->INTVECTV[i].reg = *vector;
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vector++;
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}
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}
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/**
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* \brief Write the input data (four consecutive 32-bit words).
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*
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* \param[in] module Pointer to the software instance struct
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* \param[in] input_data_buffer Pointer to an input data buffer
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*/
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void aes_write_input_data(
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struct aes_module *const module,
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const uint32_t *input_data_buffer)
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{
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uint32_t i;
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/* Validate arguments. */
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Assert(module);
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Assert(module->hw);;
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Assert(input_data_buffer);
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module->hw->DATABUFPTR.reg = 0;
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if (module->opmode == AES_CFB_MODE
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&& module->cfb_size == AES_CFB_SIZE_64){
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for (i = 0; i < 2; i++) {
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module->hw->INDATA.reg = *input_data_buffer;
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input_data_buffer++;
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}
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} else if (module->opmode == AES_CFB_MODE
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&& (module->cfb_size == AES_CFB_SIZE_32 || module->cfb_size == AES_CFB_SIZE_16)){
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module->hw->INDATA.reg = *input_data_buffer;
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} else {
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for (i = 0; i < 4; i++) {
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module->hw->INDATA.reg = *input_data_buffer;
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input_data_buffer++;
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}
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}
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}
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/**
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* \brief Read the output data.
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*
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* \note The data buffer that holds the processed data must be large enough to hold
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* four consecutive 32-bit words.
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*
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* \param[in] module Pointer to the software instance struct
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* \param[in] output_data_buffer Pointer to an output buffer
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*/
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void aes_read_output_data(
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struct aes_module *const module,
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uint32_t *output_data_buffer)
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{
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uint32_t i;
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/* Validate arguments. */
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Assert(module);
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Assert(module->hw);
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Assert(output_data_buffer);
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module->hw->DATABUFPTR.reg = 0;
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if (module->opmode == AES_CFB_MODE
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&& module->cfb_size == AES_CFB_SIZE_64){
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for (i = 0; i < 2; i++) {
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*output_data_buffer = module->hw->INDATA.reg;
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output_data_buffer++;
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}
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} else if (module->opmode == AES_CFB_MODE
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&& (module->cfb_size == AES_CFB_SIZE_32 || module->cfb_size == AES_CFB_SIZE_16)){
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*output_data_buffer = module->hw->INDATA.reg;
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} else {
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for (i = 0; i < 4; i++) {
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*output_data_buffer = module->hw->INDATA.reg;
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output_data_buffer++;
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}
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}
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}
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