278 lines
9.6 KiB
C
278 lines
9.6 KiB
C
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/**
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* \file
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*
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* \brief INTC software driver for AVR UC3 devices.
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*
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* Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Subject to your compliance with these terms, you may use Microchip
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* software and any derivatives exclusively with Microchip products.
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* It is your responsibility to comply with third party license terms applicable
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* to your use of third party software (including open source software) that
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* may accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
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* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
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* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
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* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
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* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
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* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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* \asf_license_stop
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*
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*/
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/*
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* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
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*/
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#include <avr32/io.h>
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#include "compiler.h"
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#include "preprocessor.h"
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#include "intc.h"
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/**
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* \internal
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* \brief Import the _evba symbol from exception.S
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*/
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extern void _evba;
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/**
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* \internal
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* \brief Import the symbols _int0, _int1, _int2, _int3 defined in exception.S
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*/
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extern void _int0, _int1, _int2, _int3;
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/**
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* \internal
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* \brief Values to store in the interrupt priority registers for the various
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* interrupt priority levels.
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*/
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#define IPR_INT0 ((AVR32_INTC_INT0 << AVR32_INTC_IPR_INTLEVEL_OFFSET) \
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| ((int)&_int0 - (int)&_evba))
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#define IPR_INT1 ((AVR32_INTC_INT1 << AVR32_INTC_IPR_INTLEVEL_OFFSET) \
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| ((int)&_int1 - (int)&_evba))
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#define IPR_INT2 ((AVR32_INTC_INT2 << AVR32_INTC_IPR_INTLEVEL_OFFSET) \
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| ((int)&_int2 - (int)&_evba))
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#define IPR_INT3 ((AVR32_INTC_INT3 << AVR32_INTC_IPR_INTLEVEL_OFFSET) \
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| ((int)&_int3 - (int)&_evba))
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/**
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* \internal
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* \brief Table of interrupt line handlers per interrupt group in order to
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* optimize RAM space. Each line handler table contains a set of pointers to
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* interrupt handlers.
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*/
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#if (defined __GNUC__)
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# define DECL_INT_LINE_HANDLER_TABLE(GRP, unused) \
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static volatile __int_handler \
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_int_line_handler_table_##GRP[Max(AVR32_INTC_NUM_IRQS_PER_GRP##GRP, 1)];
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#elif (defined __ICCAVR32__)
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# define DECL_INT_LINE_HANDLER_TABLE(GRP, unused) \
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static volatile __no_init __int_handler \
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_int_line_handler_table_##GRP[Max(AVR32_INTC_NUM_IRQS_PER_GRP##GRP, 1)];
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#endif
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MREPEAT(AVR32_INTC_NUM_INT_GRPS, DECL_INT_LINE_HANDLER_TABLE, ~);
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#undef DECL_INT_LINE_HANDLER_TABLE
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/**
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* \internal
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* \brief Table containing for each interrupt group the number of interrupt
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* request lines and a pointer to the table of interrupt line handlers.
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*/
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static const struct
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{
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unsigned int num_irqs;
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volatile __int_handler *_int_line_handler_table;
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} _int_handler_table[AVR32_INTC_NUM_INT_GRPS] =
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{
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#define INSERT_INT_LINE_HANDLER_TABLE(GRP, unused) \
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{AVR32_INTC_NUM_IRQS_PER_GRP##GRP, _int_line_handler_table_##GRP},
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MREPEAT(AVR32_INTC_NUM_INT_GRPS, INSERT_INT_LINE_HANDLER_TABLE, ~)
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#undef INSERT_INT_LINE_HANDLER_TABLE
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};
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/**
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* \internal
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* \brief Default interrupt handler.
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*/
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#if (defined __GNUC__)
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__attribute__((__interrupt__))
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#elif (defined __ICCAVR32__)
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__interrupt
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#endif
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static void _unhandled_interrupt(void)
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{
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// Catch unregistered interrupts.
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while (true);
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}
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/**
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* \brief Gets the interrupt handler of the current event at the \a int_level
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* interrupt priority level (called from exception.S).
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*
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* \param int_level Interrupt priority level to handle.
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*
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* \return Interrupt handler to execute.
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*/
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__int_handler _get_interrupt_handler(uint32_t int_level);
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__int_handler _get_interrupt_handler(uint32_t int_level)
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{
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/* ICR3 is mapped first, ICR0 last.
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Code in exception.S puts int_level in R12 which is used by the compiler
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to pass a single argument to a function. */
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uint32_t int_grp = AVR32_INTC.icr[AVR32_INTC_INT3 - int_level];
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uint32_t int_req = AVR32_INTC.irr[int_grp];
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/* As an interrupt may disappear while it is being fetched by the CPU
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(spurious interrupt caused by a delayed response from an MCU peripheral
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to an interrupt flag clear or interrupt disable instruction), check if
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there are remaining interrupt lines to process.
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If a spurious interrupt occurs, the status register (SR) contains an
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execution mode and interrupt level masks corresponding to a level 0
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interrupt, whatever the interrupt priority level causing the spurious
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event. This behavior has been chosen because a spurious interrupt has
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not to be a priority one and because it may not cause any trouble to
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other interrupts.
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However, these spurious interrupts place the hardware in an unstable
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state and could give problems in other/future versions of the CPU, so
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the software has to be written so that they never occur. The only safe
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way of achieving this is to always clear or disable peripheral
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interrupts with the following sequence:
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1: Mask the interrupt in the CPU by setting GM (or IxM) in SR.
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2: Perform the bus access to the peripheral register that clears or
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disables the interrupt.
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3: Wait until the interrupt has actually been cleared or disabled by the
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peripheral. This is usually performed by reading from a register in the
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same peripheral (it DOES NOT have to be the same register that was
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accessed in step 2, but it MUST be in the same peripheral), what takes
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bus system latencies into account, but peripheral internal latencies
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(generally 0 cycle) also have to be considered.
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4: Unmask the interrupt in the CPU by clearing GM (or IxM) in SR.
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Note that steps 1 and 4 are useless inside interrupt handlers as the
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corresponding interrupt level is automatically masked by IxM (unless IxM
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is explicitly cleared by the software).*/
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/* Get the right IRQ handler.
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If several interrupt lines are active in the group, the interrupt line
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with the highest number is selected. This is to be coherent with the
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prioritization of interrupt groups performed by the hardware interrupt
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controller.
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If no handler has been registered for the pending interrupt,
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_unhandled_interrupt will be selected thanks to the initialization of
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_int_line_handler_table_x by INTC_init_interrupts.
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exception.S will provide the interrupt handler with a clean interrupt
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stack frame, with nothing more pushed onto the stack. The interrupt
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handler must manage the `rete' instruction, which can be done using
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pure assembly, inline assembly or the `__attribute__((__interrupt__))'
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C function attribute.*/
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return (int_req)
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? _int_handler_table[int_grp]._int_line_handler_table[32
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- clz(int_req) - 1]
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: NULL;
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}
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/**
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* \internal
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* \brief Init EVBA address. This operation may or may not have been done by the
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* C startup process.
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*/
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static __inline__ void INTC_init_evba(void)
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{
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Set_system_register(AVR32_EVBA, (int32_t)&_evba );
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}
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/**
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* \brief Initializes the hardware interrupt controller driver.
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*
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*/
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void INTC_init_interrupts(void)
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{
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uint32_t int_grp, int_req;
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INTC_init_evba();
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// For all interrupt groups,
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for (int_grp = 0; int_grp < AVR32_INTC_NUM_INT_GRPS; int_grp++)
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{
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// For all interrupt request lines of each group,
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for (int_req = 0;
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int_req < _int_handler_table[int_grp].num_irqs;
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int_req++)
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{
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/* Assign _unhandled_interrupt as the default interrupt
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handler. */
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_int_handler_table[int_grp]
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._int_line_handler_table[int_req]
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= &_unhandled_interrupt;
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}
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/* Set the interrupt group priority register to its default
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value.
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By default, all interrupt groups are linked to the interrupt
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priority level 0 and to the interrupt vector _int0. */
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AVR32_INTC.ipr[int_grp] = IPR_INT0;
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}
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}
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/**
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* \brief Registers an interrupt handler.
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*
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* \param handler Interrupt handler to register.
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* \param irq IRQ of the interrupt handler to register.
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* \param int_level Interrupt priority level to assign to the group of this IRQ.
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*
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* \warning The interrupt handler must manage the `rete' instruction, which can
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* be done using pure assembly, inline assembly or the
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* `__attribute__((__interrupt__))' C function attribute.
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*
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* \warning If several interrupt handlers of a same group are registered with
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* different priority levels, only the latest priority level set will
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* be effective.
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*
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*/
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void INTC_register_interrupt(__int_handler handler, uint32_t irq,
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uint32_t int_level)
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{
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// Determine the group of the IRQ.
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uint32_t int_grp = irq / AVR32_INTC_MAX_NUM_IRQS_PER_GRP;
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/* Store in _int_line_handler_table_x the pointer to the interrupt
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handler, so that _get_interrupt_handler can retrieve it when the
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interrupt is vectored. */
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_int_handler_table[int_grp]
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._int_line_handler_table[irq % AVR32_INTC_MAX_NUM_IRQS_PER_GRP]
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= handler;
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/* Program the corresponding IPRX register to set the interrupt priority
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level and the interrupt vector offset that will be fetched by the core
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interrupt system.
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NOTE: The _intx functions are intermediate assembly functions between
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the core interrupt system and the user interrupt handler. */
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if (int_level == AVR32_INTC_INT0) {
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AVR32_INTC.ipr[int_grp] = IPR_INT0;
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} else if (int_level == AVR32_INTC_INT1) {
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AVR32_INTC.ipr[int_grp] = IPR_INT1;
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} else if (int_level == AVR32_INTC_INT2) {
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AVR32_INTC.ipr[int_grp] = IPR_INT2;
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} else {
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AVR32_INTC.ipr[int_grp] = IPR_INT3;
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}
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}
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