176 lines
7.6 KiB
C
176 lines
7.6 KiB
C
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//###########################################################################
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//
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// FILE: F2837xD_nmiintrupt.h
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//
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// TITLE: NMIINTRUPT Register Definitions.
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//
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//###########################################################################
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// $TI Release: F2837xD Support Library v3.05.00.00 $
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// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
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// $Copyright:
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// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#ifndef __F2837xD_NMIINTRUPT_H__
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#define __F2837xD_NMIINTRUPT_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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//---------------------------------------------------------------------------
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// NMIINTRUPT Individual Register Bit Definitions:
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struct NMICFG_BITS { // bits description
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Uint16 NMIE:1; // 0 Global NMI Enable
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Uint16 rsvd1:15; // 15:1 Reserved
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};
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union NMICFG_REG {
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Uint16 all;
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struct NMICFG_BITS bit;
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};
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struct NMIFLG_BITS { // bits description
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Uint16 NMIINT:1; // 0 NMI Interrupt Flag
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Uint16 CLOCKFAIL:1; // 1 Clock Fail Interrupt Flag
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Uint16 RAMUNCERR:1; // 2 RAM Uncorrectable Error NMI Flag
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Uint16 FLUNCERR:1; // 3 Flash Uncorrectable Error NMI Flag
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Uint16 CPU1HWBISTERR:1; // 4 HW BIST Error NMI Flag
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Uint16 CPU2HWBISTERR:1; // 5 HW BIST Error NMI Flag
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Uint16 PIEVECTERR:1; // 6 PIE Vector Fetch Error Flag
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Uint16 rsvd1:1; // 7 Reserved
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Uint16 rsvd2:1; // 8 Reserved
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Uint16 CPU2WDRSn:1; // 9 CPU2 WDRSn Reset Indication Flag
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Uint16 CPU2NMIWDRSn:1; // 10 CPU2 NMIWDRSn Reset Indication Flag
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Uint16 rsvd3:1; // 11 Reserved
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Uint16 rsvd4:4; // 15:12 Reserved
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};
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union NMIFLG_REG {
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Uint16 all;
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struct NMIFLG_BITS bit;
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};
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struct NMIFLGCLR_BITS { // bits description
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Uint16 NMIINT:1; // 0 NMIINT Flag Clear
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Uint16 CLOCKFAIL:1; // 1 CLOCKFAIL Flag Clear
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Uint16 RAMUNCERR:1; // 2 RAMUNCERR Flag Clear
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Uint16 FLUNCERR:1; // 3 FLUNCERR Flag Clear
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Uint16 CPU1HWBISTERR:1; // 4 CPU1HWBISTERR Flag Clear
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Uint16 CPU2HWBISTERR:1; // 5 CPU2HWBISTERR Flag Clear
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Uint16 PIEVECTERR:1; // 6 PIEVECTERR Flag Clear
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Uint16 rsvd1:1; // 7 Reserved
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Uint16 rsvd2:1; // 8 Reserved
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Uint16 CPU2WDRSn:1; // 9 CPU2WDRSn Flag Clear
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Uint16 CPU2NMIWDRSn:1; // 10 CPU2NMIWDRSn Flag Clear
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Uint16 OVF:1; // 11 OVF Flag Clear
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Uint16 rsvd3:4; // 15:12 Reserved
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};
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union NMIFLGCLR_REG {
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Uint16 all;
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struct NMIFLGCLR_BITS bit;
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};
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struct NMIFLGFRC_BITS { // bits description
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Uint16 rsvd1:1; // 0 Reserved
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Uint16 CLOCKFAIL:1; // 1 CLOCKFAIL Flag Force
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Uint16 RAMUNCERR:1; // 2 RAMUNCERR Flag Force
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Uint16 FLUNCERR:1; // 3 FLUNCERR Flag Force
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Uint16 CPU1HWBISTERR:1; // 4 CPU1HWBISTERR Flag Force
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Uint16 CPU2HWBISTERR:1; // 5 CPU2HWBISTERR Flag Force
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Uint16 PIEVECTERR:1; // 6 PIEVECTERR Flag Force
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Uint16 rsvd2:1; // 7 Reserved
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Uint16 rsvd3:1; // 8 Reserved
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Uint16 CPU2WDRSn:1; // 9 CPU2WDRSn Flag Force
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Uint16 CPU2NMIWDRSn:1; // 10 CPU2NMIWDRSn Flag Force
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Uint16 OVF:1; // 11 OVF Flag Force
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Uint16 rsvd4:4; // 15:12 Reserved
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};
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union NMIFLGFRC_REG {
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Uint16 all;
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struct NMIFLGFRC_BITS bit;
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};
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struct NMISHDFLG_BITS { // bits description
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Uint16 rsvd1:1; // 0 Reserved
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Uint16 CLOCKFAIL:1; // 1 Shadow CLOCKFAIL Flag
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Uint16 RAMUNCERR:1; // 2 Shadow RAMUNCERR Flag
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Uint16 FLUNCERR:1; // 3 Shadow FLUNCERR Flag
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Uint16 CPU1HWBISTERR:1; // 4 Shadow CPU1HWBISTERR Flag
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Uint16 CPU2HWBISTERR:1; // 5 Shadow CPU2HWBISTERR Flag
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Uint16 PIEVECTERR:1; // 6 Shadow PIEVECTERR Flag
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Uint16 rsvd2:1; // 7 Reserved
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Uint16 rsvd3:1; // 8 Reserved
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Uint16 CPU2WDRSn:1; // 9 Shadow CPU2WDRSn Flag
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Uint16 CPU2NMIWDRSn:1; // 10 Shadow CPU2NMIWDRSn Flag
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Uint16 OVF:1; // 11 Shadow OVF Flag
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Uint16 rsvd4:4; // 15:12 Reserved
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};
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union NMISHDFLG_REG {
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Uint16 all;
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struct NMISHDFLG_BITS bit;
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};
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struct NMI_INTRUPT_REGS {
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union NMICFG_REG NMICFG; // NMI Configuration Register
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union NMIFLG_REG NMIFLG; // NMI Flag Register (XRSn Clear)
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union NMIFLGCLR_REG NMIFLGCLR; // NMI Flag Clear Register
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union NMIFLGFRC_REG NMIFLGFRC; // NMI Flag Force Register
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Uint16 NMIWDCNT; // NMI Watchdog Counter Register
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Uint16 NMIWDPRD; // NMI Watchdog Period Register
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union NMISHDFLG_REG NMISHDFLG; // NMI Shadow Flag Register
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};
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//---------------------------------------------------------------------------
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// NMIINTRUPT External References & Function Declarations:
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//
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#ifdef CPU1
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extern volatile struct NMI_INTRUPT_REGS NmiIntruptRegs;
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#endif
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#ifdef CPU2
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extern volatile struct NMI_INTRUPT_REGS NmiIntruptRegs;
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#endif
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#ifdef __cplusplus
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}
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#endif /* extern "C" */
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#endif
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//===========================================================================
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// End of file.
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//===========================================================================
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