2021-09-09 20:31:17 +08:00
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/*
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2023-02-11 08:14:33 +08:00
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* Copyright (c) 2006-2023, RT-Thread Development Team
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2021-09-09 20:31:17 +08:00
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-08-20 breo.com first version
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*/
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#ifndef __BOARD_H__
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#define __BOARD_H__
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#include <n32g45x.h>
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#include "n32_msp.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Just only support for N32G452XX */
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#define N32_FLASH_START_ADRESS ((uint32_t)0x08000000)
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#define FLASH_PAGE_SIZE (2 * 1024)
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#define N32_FLASH_SIZE (256 * 1024)
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#define N32_FLASH_END_ADDRESS ((uint32_t)(N32_FLASH_START_ADRESS + N32_FLASH_SIZE))
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/* Internal SRAM memory size[Kbytes] <80>, Default: 80*/
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2022-01-18 16:51:46 +08:00
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#define N32_SRAM_SIZE (144)
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2021-09-09 20:31:17 +08:00
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#define N32_SRAM_END (0x20000000 + N32_SRAM_SIZE * 1024)
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2021-12-30 03:14:07 +08:00
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#if defined(__ARMCC_VERSION)
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2021-09-09 20:31:17 +08:00
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extern int Image$$RW_IRAM1$$ZI$$Limit;
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#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
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#elif __ICCARM__
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#pragma section="CSTACK"
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#define HEAP_BEGIN (__segment_end("CSTACK"))
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#else
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extern int __bss_end;
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#define HEAP_BEGIN ((void *)&__bss_end)
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#endif
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#define HEAP_END N32_SRAM_END
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#ifdef __cplusplus
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}
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#endif
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#endif /* __BOARD_H__ */
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