2020-03-09 15:10:16 +08:00
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/*
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2021-03-14 15:15:52 +08:00
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* Copyright (c) 2006-2021, RT-Thread Development Team
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2020-03-09 15:10:16 +08:00
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-01-14 shelton first version
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*/
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#ifndef _DRV_SDIO_H
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#define _DRV_SDIO_H
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#include <rtthread.h>
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#include "rtdevice.h"
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#include <rthw.h>
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#include <string.h>
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#include <drivers/mmcsd_core.h>
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#include <drivers/sdio.h>
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#include "at32f4xx.h"
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#define SDCARD_INSTANCE_TYPE SDIO_Type
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#define SDCARD_INSTANCE SDIO1
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#define SDIO_BUFF_SIZE 4096
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#define SDIO_ALIGN_LEN 32
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#ifndef SDIO_MAX_FREQ
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#define SDIO_MAX_FREQ (1000000)
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#endif
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#ifndef SDIO_BASE_ADDRESS
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#define SDIO_BASE_ADDRESS SDIO1_BASE
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#endif
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#ifndef SDIO_CLOCK_FREQ
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#define SDIO_CLOCK_FREQ (48U * 1000 * 1000)
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#endif
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#ifndef SDIO_BUFF_SIZE
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#define SDIO_BUFF_SIZE (4096)
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#endif
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#ifndef SDIO_ALIGN_LEN
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#define SDIO_ALIGN_LEN (32)
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#endif
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#ifndef SDIO_MAX_FREQ
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#define SDIO_MAX_FREQ (24 * 1000 * 1000)
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#endif
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#define HW_SDIO_IT_CCRCFAIL (0x01U << 0)
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#define HW_SDIO_IT_DCRCFAIL (0x01U << 1)
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#define HW_SDIO_IT_CTIMEOUT (0x01U << 2)
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#define HW_SDIO_IT_DTIMEOUT (0x01U << 3)
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#define HW_SDIO_IT_TXUNDERR (0x01U << 4)
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#define HW_SDIO_IT_RXOVERR (0x01U << 5)
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#define HW_SDIO_IT_CMDREND (0x01U << 6)
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#define HW_SDIO_IT_CMDSENT (0x01U << 7)
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#define HW_SDIO_IT_DATAEND (0x01U << 8)
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#define HW_SDIO_IT_STBITERR (0x01U << 9)
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#define HW_SDIO_IT_DBCKEND (0x01U << 10)
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#define HW_SDIO_IT_CMDACT (0x01U << 11)
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#define HW_SDIO_IT_TXACT (0x01U << 12)
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#define HW_SDIO_IT_RXACT (0x01U << 13)
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#define HW_SDIO_IT_TXFIFOHE (0x01U << 14)
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#define HW_SDIO_IT_RXFIFOHF (0x01U << 15)
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#define HW_SDIO_IT_TXFIFOF (0x01U << 16)
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#define HW_SDIO_IT_RXFIFOF (0x01U << 17)
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#define HW_SDIO_IT_TXFIFOE (0x01U << 18)
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#define HW_SDIO_IT_RXFIFOE (0x01U << 19)
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#define HW_SDIO_IT_TXDAVL (0x01U << 20)
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#define HW_SDIO_IT_RXDAVL (0x01U << 21)
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#define HW_SDIO_IT_SDIOIT (0x01U << 22)
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#define HW_SDIO_ERRORS \
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(HW_SDIO_IT_CCRCFAIL | HW_SDIO_IT_CTIMEOUT | \
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HW_SDIO_IT_DCRCFAIL | HW_SDIO_IT_DTIMEOUT | \
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HW_SDIO_IT_RXOVERR | HW_SDIO_IT_TXUNDERR)
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#define HW_SDIO_POWER_OFF (0x00U)
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#define HW_SDIO_POWER_UP (0x02U)
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#define HW_SDIO_POWER_ON (0x03U)
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#define HW_SDIO_FLOW_ENABLE (0x01U << 14)
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#define HW_SDIO_BUSWIDE_1B (0x00U << 11)
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#define HW_SDIO_BUSWIDE_4B (0x01U << 11)
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#define HW_SDIO_BUSWIDE_8B (0x02U << 11)
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#define HW_SDIO_BYPASS_ENABLE (0x01U << 10)
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#define HW_SDIO_IDLE_ENABLE (0x01U << 9)
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#define HW_SDIO_CLK_ENABLE (0x01U << 8)
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#define HW_SDIO_SUSPEND_CMD (0x01U << 11)
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#define HW_SDIO_CPSM_ENABLE (0x01U << 10)
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#define HW_SDIO_WAIT_END (0x01U << 9)
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#define HW_SDIO_WAIT_INT (0x01U << 8)
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#define HW_SDIO_RESPONSE_NO (0x00U << 6)
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#define HW_SDIO_RESPONSE_SHORT (0x01U << 6)
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#define HW_SDIO_RESPONSE_LONG (0x03U << 6)
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#define HW_SDIO_DATA_LEN_MASK (0x01FFFFFFU)
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#define HW_SDIO_IO_ENABLE (0x01U << 11)
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#define HW_SDIO_RWMOD_CK (0x01U << 10)
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#define HW_SDIO_RWSTOP_ENABLE (0x01U << 9)
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#define HW_SDIO_RWSTART_ENABLE (0x01U << 8)
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#define HW_SDIO_DBLOCKSIZE_1 (0x00U << 4)
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#define HW_SDIO_DBLOCKSIZE_2 (0x01U << 4)
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#define HW_SDIO_DBLOCKSIZE_4 (0x02U << 4)
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#define HW_SDIO_DBLOCKSIZE_8 (0x03U << 4)
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#define HW_SDIO_DBLOCKSIZE_16 (0x04U << 4)
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#define HW_SDIO_DBLOCKSIZE_32 (0x05U << 4)
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#define HW_SDIO_DBLOCKSIZE_64 (0x06U << 4)
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#define HW_SDIO_DBLOCKSIZE_128 (0x07U << 4)
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#define HW_SDIO_DBLOCKSIZE_256 (0x08U << 4)
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#define HW_SDIO_DBLOCKSIZE_512 (0x09U << 4)
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#define HW_SDIO_DBLOCKSIZE_1024 (0x0AU << 4)
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#define HW_SDIO_DBLOCKSIZE_2048 (0x0BU << 4)
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#define HW_SDIO_DBLOCKSIZE_4096 (0x0CU << 4)
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#define HW_SDIO_DBLOCKSIZE_8192 (0x0DU << 4)
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#define HW_SDIO_DBLOCKSIZE_16384 (0x0EU << 4)
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#define HW_SDIO_DMA_ENABLE (0x01U << 3)
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#define HW_SDIO_STREAM_ENABLE (0x01U << 2)
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#define HW_SDIO_TO_HOST (0x01U << 1)
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#define HW_SDIO_DPSM_ENABLE (0x01U << 0)
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#define HW_SDIO_DATATIMEOUT (0xF0000000U)
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struct at32_sdio
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{
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volatile rt_uint32_t power;
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volatile rt_uint32_t clkcr;
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volatile rt_uint32_t arg;
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volatile rt_uint32_t cmd;
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volatile rt_uint32_t respcmd;
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volatile rt_uint32_t resp1;
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volatile rt_uint32_t resp2;
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volatile rt_uint32_t resp3;
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volatile rt_uint32_t resp4;
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volatile rt_uint32_t dtimer;
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volatile rt_uint32_t dlen;
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volatile rt_uint32_t dctrl;
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volatile rt_uint32_t dcount;
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volatile rt_uint32_t sta;
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volatile rt_uint32_t icr;
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volatile rt_uint32_t mask;
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volatile rt_uint32_t reserved0[2];
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volatile rt_uint32_t fifocnt;
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volatile rt_uint32_t reserved1[13];
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volatile rt_uint32_t fifo;
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};
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typedef rt_err_t (*dma_txconfig)(rt_uint32_t *src, rt_uint32_t *dst, int size);
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typedef rt_err_t (*dma_rxconfig)(rt_uint32_t *src, rt_uint32_t *dst, int size);
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typedef rt_uint32_t (*sdio_clk_get)(struct at32_sdio *hw_sdio);
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#define SDIO_BUS_CONFIG \
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{ \
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.Instance = SDIO1, \
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.dma_rx.dma_rcc = RCC_AHBEN_DMA2EN, \
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.dma_tx.dma_rcc = RCC_AHBEN_DMA2EN, \
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.dma_rx.Instance = DMA2_Channel4, \
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.dma_rx.dma_irq = DMA2_Channel4_5_IRQn, \
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.dma_tx.Instance = DMA2_Channel4, \
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.dma_tx.dma_irq = DMA2_Channel4_5_IRQn, \
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}
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struct dma_config {
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DMA_Channel_Type *Instance;
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rt_uint32_t dma_rcc;
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IRQn_Type dma_irq;
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};
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struct at32_sdio_des
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{
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struct at32_sdio *hw_sdio;
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dma_txconfig txconfig;
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dma_rxconfig rxconfig;
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sdio_clk_get clk_get;
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};
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struct at32_sdio_config
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{
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SDCARD_INSTANCE_TYPE *Instance;
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struct dma_config dma_rx, dma_tx;
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};
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/* at32 sdio dirver class */
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struct at32_sdio_class
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{
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struct at32_sdio_des *des;
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const struct at32_sdio_config *cfg;
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struct rt_mmcsd_host host;
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struct
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{
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DMA_Channel_Type* handle_rx;
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DMA_Channel_Type* handle_tx;
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} dma;
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};
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extern void at32_mmcsd_change(void);
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#endif
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