455 lines
19 KiB
C
455 lines
19 KiB
C
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/**
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******************************************************************************
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* @brief EXMC header file of the firmware library.
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __GD32F10X_EXMC_H
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#define __GD32F10X_EXMC_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "gd32f10x.h"
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/** @addtogroup GD32F10x_Firmware
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* @{
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*/
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/** @addtogroup EXMC
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* @{
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*/
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/** @defgroup EXMC_Exported_Types
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* @{
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*/
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/**
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* @brief Initial Timing Parameters For NOR/SRAM Banks
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*/
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typedef struct {
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uint32_t EXMC_AsynAccessMode; /*!< The asynchronous access mode, detailed in @ref EXMC_AsynAccess_Mode*/
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uint32_t EXMC_SynDataLatency; /*!< The number of CLK cycles to configure the data latency,
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which may assume a value between 0x0 and 0xF. */
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uint32_t EXMC_SynCLKDivision; /*!< The number of HCLK cycles to configure the clock divide ratio,
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which can be a value between 0x0 and 0xF. */
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uint32_t EXMC_BusLatency; /*!< The number of HCLK cycles to configure the bus latency,
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which can be a value between 0x0 and 0xF. */
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uint32_t EXMC_AsynDataSetupTime; /*!< The number of HCLK cycles to configure the data setup time
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while in the asynchronous access mode, which can be a value
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between 0x00 and 0xFF. */
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uint32_t EXMC_AsynAddressHoldTime; /*!< The number of HCLK cycles to configure the address hold time
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while in the asynchronous access mode, which can be a value
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between 0x0 and 0xF. */
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uint32_t EXMC_AsynAddressSetupTime; /*!< The number of HCLK cycles to configure the data setup time
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while in the asynchronous access mode, which can be a value
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between 0x0 and 0xF. */
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} EXMC_NORSRAMTimingInitPara;
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/**
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* @brief EXMC NOR/SRAM Init structure definition
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*/
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typedef struct {
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uint32_t EXMC_NORSRAMBank; /*!< The specified region of NORSRAM Bank1,
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choose one from @ref EXMC_NORSRAMBank. */
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uint32_t EXMC_WriteMode; /*!< The write mode, details in @ref EXMC_WriteMode. */
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uint32_t EXMC_ExtendedMode; /*!< Enable or Disable the extended mode, details in
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@ref EXMC_ExtendedMode. */
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uint32_t EXMC_AsynWait; /*!< Enable or disable the asynchronous wait feature,detial
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in @ref EXMC_AsynWait. */
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uint32_t EXMC_NWAITSignal; /*!< Enable or Disable the NWAIT signal while in synchronous
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bust mode, details in @ref EXMC_NWAITSignal. */
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uint32_t EXMC_MemoryWrite; /*!< Enable or Disable the write operation, details in
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@ref EXMC_MemoryWrite. */
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uint32_t EXMC_NWAITConfig; /*!< NWAIT signal configuration, details in @ref EXMC_NWAITConfig */
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uint32_t EXMC_WrapBurstMode; /*!< Enable or Disable the wrap burst mode, details in
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@ref EXMC_WrapBurstMode. */
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uint32_t EXMC_NWAITPolarity; /*!< Specifies the polarity of NWAIT signal from memory,
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details in @ref EXMC_NWAITPolarity. */
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uint32_t EXMC_BurstMode; /*!< Enable or Disable the burst mode, details in
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@ref EXMC_BurstMode. */
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uint32_t EXMC_DatabusWidth; /*!< Specifies the databus width of external memory,
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details in @ref EXMC_DatabusWidth. */
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uint32_t EXMC_MemoryType; /*!< Specifies the type of external memory, details in
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@ref EXMC_MemoryType. */
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uint32_t EXMC_AddressDataMux; /*!< Specifies whether the data bus and address bus are multiplexed
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or not,details in @ref EXMC_AddressDataMux. */
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EXMC_NORSRAMTimingInitPara *EXMC_ReadWriteTimingParaStruct; /*!< The struct EXMC_NORSRAMTimingInitPara pointer,which is
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used to define the timing parameters for read and write
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if the ExtendedMode is not used or define the timing
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parameters for read if the ExtendedMode is used. */
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EXMC_NORSRAMTimingInitPara *EXMC_WriteTimingParaStruct; /*!< The struct EXMC_NORSRAMTimingInitPara pointer,which is
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only used to define the timing parameters for write when
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the ExtendedMode is used. */
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} EXMC_NORSRAMInitPara;
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/**
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* @brief Timing parameters For EXMC NAND and PCCARD Banks
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*/
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typedef struct {
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uint32_t EXMC_DatabusHiZTime; /*!< The number of HCLK cycles to configure the dadtabus HiZ time
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for write operation, which can be a value between 0x00 and 0xFF. */
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uint32_t EXMC_HoldTime; /*!< The number of HCLK cycles to configure the address hold time
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(or the data hold time for write operation),which can be a value
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between 0x00 and 0xFF. */
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uint32_t EXMC_WaitTime; /*!< The number of HCLK cycles to configure the minimum wait time,
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which can be a value between 0x00 and 0xFF. */
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uint32_t EXMC_SetupTime; /*!< The number of HCLK cycles to configure the address setup time ,
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which can be a value between 0x00 and 0xFF. */
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} EXMC_NAND_PCCARDTimingInitPara;
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/**
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* @brief EXMC NAND Init structure definition
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*/
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typedef struct {
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uint32_t EXMC_NANDBank; /*!< The specified Bank of NAND FLASH, choose one
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from @ref EXMC_NANDBank. */
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uint32_t EXMC_ECCSize; /*!< The page size for the ECC calculation,details
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in @ref EXMC_ECCSize. */
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uint32_t EXMC_ATRLatency; /*!< The number of HCLK cycles to configure the
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latency of ALE low to RB low, which can be a
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value between 0x0 and 0xF. */
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uint32_t EXMC_CTRLatency; /*!< The number of HCLK cycles to configure the
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latency of CLE low to RB low, which can be a
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value between 0x0 and 0xF. */
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uint32_t EXMC_ECCLogic; /*!< Enable or Disable the ECC calculation logic,
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details in @ref EXMC_ECCLogic. */
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uint32_t EXMC_DatabusWidth; /*!< the NAND flash databus width, details in
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@ref EXMC_DatabusWidth. */
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uint32_t EXMC_WaitFeature; /*!< Enables or Disables the Wait feature,details
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in @ref EXMC_WaitFeature. */
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EXMC_NAND_PCCARDTimingInitPara *EXMC_CommonSpaceTimingParaStruct; /*!< The struct EXMC_NAND_PCCARDTimingInitPara
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pointer, which is used to define the timing
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parameters for NAND flash Common Space. */
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EXMC_NAND_PCCARDTimingInitPara *EXMC_AttributeSpaceTimingParaStruct; /*!< The struct EXMC_NAND_PCCARDTimingInitPara
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pointer, which is used to define the timing
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parameters for NAND flash Attribute Space. */
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} EXMC_NANDInitPara;
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/**
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* @brief EXMC PCCARD Init structure definition
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*/
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typedef struct {
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uint32_t EXMC_ATRLatency; /*!< The number of HCLK cycles to configure
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the latency of ALE low to RB low, which can
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be a value between 0x0 and 0xF. */
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uint32_t EXMC_CTRLatency; /*!< The number of HCLK cycles to configure
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the latency of CLE low to RB low, which can
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be a value between 0x0 and 0xF. */
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uint32_t EXMC_WaitFeature; /*!< Enables or Disables the Wait feature,details
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in @ref EXMC_WaitFeature. */
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EXMC_NAND_PCCARDTimingInitPara *EXMC_CommonSpaceTimingParaStruct; /*!< The struct EXMC_NAND_PCCARDTimingInitPara
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pointer, which is used to define the timing
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parameters for PC CARD Common Space. */
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EXMC_NAND_PCCARDTimingInitPara *EXMC_AttributeSpaceTimingParaStruct; /*!< The struct EXMC_NAND_PCCARDTimingInitPara
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pointer, which is used to define the timing
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parameters for PC CARD Attribute Space. */
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EXMC_NAND_PCCARDTimingInitPara *EXMC_IOSpaceTimingParaStruct; /*!< The struct EXMC_NAND_PCCARDTimingInitPara
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pointer, which is used to define the timing
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parameters for PC CARD I/O Space. */
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} EXMC_PCCARDInitPara;
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/**
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* @}
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*/
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/** @defgroup EXMC_Exported_Constants
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* @{
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*/
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/** @defgroup EXMC_NORSRAMBank
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* @{
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*/
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#define EXMC_BANK1_NORSRAM1 ((uint32_t)0x00000001)
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#define EXMC_BANK1_NORSRAM2 ((uint32_t)0x00000002)
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#define EXMC_BANK1_NORSRAM3 ((uint32_t)0x00000003)
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#define EXMC_BANK1_NORSRAM4 ((uint32_t)0x00000004)
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/**
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* @}
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*/
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/** @defgroup EXMC_NANDBank
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* @{
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*/
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#define EXMC_BANK2_NAND ((uint32_t)0x00000010)
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#define EXMC_BANK3_NAND ((uint32_t)0x00000100)
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/**
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* @}
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*/
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/** @defgroup EXMC_PCCARD_Bank
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* @{
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*/
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#define EXMC_BANK4_PCCARD ((uint32_t)0x00001000)
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/**
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* @}
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*/
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/** @defgroup NORSRAM_Controller
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* @{
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*/
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/** @defgroup EXMC_AddressDataMux
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* @{
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*/
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#define EXMC_ADDRESS_DATA_MUX_DISABLE ((uint32_t)0x00000000)
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#define EXMC_ADDRESS_DATA_MUX_ENABLE ((uint32_t)0x00000002)
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/**
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* @}
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*/
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/** @defgroup EXMC_MemoryType
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* @{
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*/
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#define EXMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
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#define EXMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004)
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#define EXMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008)
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/**
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* @}
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*/
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/** @defgroup EXMC_DatabusWidth
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* @{
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*/
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#define EXMC_DATABUS_WIDTH_8B ((uint32_t)0x00000000)
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#define EXMC_DATABUS_WIDTH_16B ((uint32_t)0x00000010)
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/**
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* @}
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*/
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/** @defgroup EXMC_NORFlash_Access
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* @{
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*/
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#define EXMC_NORFLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
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#define EXMC_NORFLASH_ACCESS_ENABLE ((uint32_t)0x00000040)
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/**
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* @}
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*/
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/** @defgroup EXMC_BurstMode
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* @{
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*/
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#define EXMC_BURST_MODE_DISABLE ((uint32_t)0x00000000)
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#define EXMC_BURST_MODE_ENABLE ((uint32_t)0x00000100)
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/**
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* @}
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*/
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/** @defgroup EXMC_AsynWait
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* @{
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*/
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#define EXMC_ASYN_WAIT_DISABLE ((uint32_t)0x00000000)
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#define EXMC_ASYN_WAIT_ENABLE ((uint32_t)0x00008000)
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/**
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* @}
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*/
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/** @defgroup EXMC_NWAITPolarity
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* @{
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*/
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#define EXMC_NWAIT_POLARITY_LOW ((uint32_t)0x00000000)
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#define EXMC_NWAIT_POLARITY_HIGH ((uint32_t)0x00000200)
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/**
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* @}
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*/
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/** @defgroup EXMC_WrapBurstMode
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* @{
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*/
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#define EXMC_WRAP_BURST_MODE_DISABLE ((uint32_t)0x00000000)
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#define EXMC_WRAP_BURST_MODE_ENABLE ((uint32_t)0x00000400)
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/**
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* @}
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*/
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/** @defgroup EXMC_NWAITConfig
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* @{
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*/
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#define EXMC_NWAIT_CONFIG_BEFORE ((uint32_t)0x00000000)
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#define EXMC_NWAIT_CONFIG_DURING ((uint32_t)0x00000800)
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/**
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* @}
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*/
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/** @defgroup EXMC_MemoryWrite
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* @{
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*/
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#define EXMC_MEMORY_WRITE_DISABLE ((uint32_t)0x00000000)
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#define EXMC_MEMORY_WRITE_ENABLE ((uint32_t)0x00001000)
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/**
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* @}
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*/
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/** @defgroup EXMC_NWAITSignal
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* @{
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*/
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#define EXMC_NWAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
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#define EXMC_NWAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
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/**
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* @}
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*/
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/** @defgroup EXMC_ExtendedMode
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* @{
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*/
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#define EXMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
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#define EXMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
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/**
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* @}
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*/
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/** @defgroup EXMC_WriteMode
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* @{
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*/
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#define EXMC_ASYN_WRITE ((uint32_t)0x00000000)
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#define EXMC_SYN_WRITE ((uint32_t)0x00080000)
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/**
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* @}
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*/
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/** @defgroup EXMC_AsynAccess_Mode
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* @{
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*/
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#define EXMC_ACCESS_MODE_A ((uint32_t)0x00000000)
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#define EXMC_ACCESS_MODE_B ((uint32_t)0x10000000)
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#define EXMC_ACCESS_MODE_C ((uint32_t)0x20000000)
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#define EXMC_ACCESS_MODE_D ((uint32_t)0x30000000)
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/**
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* @}
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*/
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/**
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* @}
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*/
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/** @defgroup NAND_PCCARD_Controller
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* @{
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*/
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/** @defgroup EXMC_WaitFeature
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* @{
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*/
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#define EXMC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
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#define EXMC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
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/**
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* @}
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||
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*/
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||
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||
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/** @defgroup EXMC_ECCLogic
|
||
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* @{
|
||
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*/
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||
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#define EXMC_ECC_LOGIC_DISABLE ((uint32_t)0x00000000)
|
||
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|
#define EXMC_ECC_LOGIC_ENABLE ((uint32_t)0x00000040)
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
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|
|
||
|
|
/** @defgroup EXMC_ECCSize
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define EXMC_ECC_SIZE_256BYTES ((uint32_t)0x00000000)
|
||
|
|
#define EXMC_ECC_SIZE_512BYTES ((uint32_t)0x00020000)
|
||
|
|
#define EXMC_ECC_SIZE_1024BYTES ((uint32_t)0x00040000)
|
||
|
|
#define EXMC_ECC_SIZE_2048BYTES ((uint32_t)0x00060000)
|
||
|
|
#define EXMC_ECC_SIZE_4096BYTES ((uint32_t)0x00080000)
|
||
|
|
#define EXMC_ECC_SIZE_8192BYTES ((uint32_t)0x000A0000)
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup EXMC_Interrupt_Source
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define EXMC_INT_RISE ((uint32_t)0x00000008)
|
||
|
|
#define EXMC_INT_LEVEL ((uint32_t)0x00000010)
|
||
|
|
#define EXMC_INT_FALL ((uint32_t)0x00000020)
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup EXMC_FLAG
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define EXMC_FLAG_RISE ((uint32_t)0x00000001)
|
||
|
|
#define EXMC_FLAG_LEVEL ((uint32_t)0x00000002)
|
||
|
|
#define EXMC_FLAG_FALL ((uint32_t)0x00000004)
|
||
|
|
#define EXMC_FLAG_FIFOE ((uint32_t)0x00000040)
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup EXMC_Exported_Functions
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
void EXMC_NORSRAM_DeInit(uint32_t EXMC_NORSRAMBank);
|
||
|
|
void EXMC_NAND_DeInit(uint32_t EXMC_NANDBank);
|
||
|
|
void EXMC_PCCARD_DeInit(void);
|
||
|
|
void EXMC_NORSRAM_Init(EXMC_NORSRAMInitPara *EXMC_NORSRAMInitParaStruct);
|
||
|
|
void EXMC_NAND_Init(EXMC_NANDInitPara *EXMC_NANDInitParaStruct);
|
||
|
|
void EXMC_PCCARD_Init(EXMC_PCCARDInitPara *EXMC_PCCARDInitParaStruct);
|
||
|
|
void EXMC_NORSRAMStruct_Init(EXMC_NORSRAMInitPara *EXMC_NORSRAMInitParaStruct);
|
||
|
|
void EXMC_NANDStruct_Init(EXMC_NANDInitPara *EXMC_NANDInitParaStruct);
|
||
|
|
void EXMC_PCCARDStruct_Init(EXMC_PCCARDInitPara *EXMC_PCCARDInitParaStruct);
|
||
|
|
void EXMC_NORSRAM_Enable(uint32_t EXMC_NORSRAMBank, TypeState NewValue);
|
||
|
|
void EXMC_NAND_Enable(uint32_t EXMC_NANDBank, TypeState NewValue);
|
||
|
|
void EXMC_PCCARD_Enable(TypeState NewValue);
|
||
|
|
void EXMC_NANDECC_Enable(uint32_t EXMC_NANDBank, TypeState NewValue);
|
||
|
|
uint32_t EXMC_GetECC(uint32_t EXMC_NANDBank);
|
||
|
|
void EXMC_INTConfig(uint32_t EXMC_PCNANDBank, uint32_t EXMC_INT, TypeState NewValue);
|
||
|
|
TypeState EXMC_GetBitState(uint32_t EXMC_PCNANDBank, uint32_t EXMC_FLAG);
|
||
|
|
void EXMC_ClearBitState(uint32_t EXMC_PCNANDBank, uint32_t EXMC_FLAG);
|
||
|
|
TypeState EXMC_GetIntBitState(uint32_t EXMC_PCNANDBank, uint32_t EXMC_INT);
|
||
|
|
void EXMC_ClearIntBitState(uint32_t EXMC_PCNANDBank, uint32_t EXMC_INT);
|
||
|
|
|
||
|
|
#ifdef __cplusplus
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif /*__GD32F10x_EXMC_H */
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|