434 lines
12 KiB
C
434 lines
12 KiB
C
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/*
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* Copyright (c) 2022 hpmicro
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Change Logs:
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* Date Author Notes
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* 2022-02-23 hpmicro First version
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* 2022-07-19 hpmicro Fixed the multi-block read/write issue
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*/
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#include <rtthread.h>
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#ifdef BSP_USING_SDXC
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#include <rthw.h>
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#include <rtdevice.h>
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#include <rtdbg.h>
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#include "board.h"
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#include "hpm_sdxc_drv.h"
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#include "hpm_l1c_drv.h"
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#define CACHE_LINESIZE HPM_L1C_CACHELINE_SIZE
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#define SDXC_ADMA_TABLE_WORDS (2U)
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#define SDXC_AMDA2_ADDR_ALIGN (4U)
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#define SDXC_DATA_TIMEOUT (0xFU)
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#define SDXC_CACHELINE_ALIGN_DOWN(x) ((uint32_t)(x) & ~((uint32_t)(CACHE_LINESIZE) - 1UL))
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#define SDXC_CACHELINE_ALIGN_UP(x) SDXC_CACHELINE_ALIGN_DOWN((uint32_t)(x) + (uint32_t)(CACHE_LINESIZE) - 1U)
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#define SDXC_IS_CACHELINE_ALIGNED(n) ((uint32_t)(n) % (uint32_t)(CACHE_LINESIZE) == 0U)
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struct hpm_mmcsd
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{
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struct rt_mmcsd_host *host;
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struct rt_mmcsd_req *req;
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struct rt_mmcsd_cmd *cmd;
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struct rt_timer *timer;
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rt_uint32_t *buf;
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SDXC_Type *sdxc_base;
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int32_t irq_num;
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uint32_t *sdxc_adma2_table;
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};
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static void hpm_sdmmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req);
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static void hpm_sdmmc_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg);
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static void hpm_sdmmc_enable_sdio_irq(struct rt_mmcsd_host *host, rt_int32_t en);
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static void hpm_sdmmc_host_recovery(SDXC_Type *base);
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static const struct rt_mmcsd_host_ops hpm_mmcsd_host_ops =
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{
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.request = hpm_sdmmc_request,
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.set_iocfg = hpm_sdmmc_set_iocfg,
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.get_card_status = NULL,
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.enable_sdio_irq = NULL, // Do not use the interrupt mode, use DMA instead
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};
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/* Place the ADMA2 table to non-cacheable region */
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ATTR_PLACE_AT_NONCACHEABLE static uint32_t s_sdxc_adma2_table[SDXC_ADMA_TABLE_WORDS];
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/**
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* !@brief SDMMC request implementation based on HPMicro SDXC Host
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*/
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static void hpm_sdmmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
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{
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struct hpm_mmcsd *mmcsd;
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struct rt_mmcsd_cmd *cmd;
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struct rt_mmcsd_data *data;
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sdxc_adma_config_t adma_config = { 0 };
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sdxc_xfer_t xfer = { 0 };
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sdxc_command_t sdxc_cmd = { 0 };
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sdxc_data_t sdxc_data = { 0 };
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uint32_t *aligned_buf = NULL;
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hpm_stat_t err = status_invalid_argument;
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RT_ASSERT(host != RT_NULL);
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RT_ASSERT(host->private_data != RT_NULL);
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RT_ASSERT(req != RT_NULL);
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RT_ASSERT(req->cmd != RT_NULL);
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mmcsd = (struct hpm_mmcsd *) host->private_data;
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cmd = req->cmd;
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data = cmd->data;
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/* configure command */
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sdxc_cmd.cmd_index = cmd->cmd_code;
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sdxc_cmd.cmd_argument = cmd->arg;
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if (cmd->cmd_code == STOP_TRANSMISSION)
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{
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sdxc_cmd.cmd_type = sdxc_cmd_type_abort_cmd;
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}
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else
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{
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sdxc_cmd.cmd_type = sdxc_cmd_type_normal_cmd;
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}
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switch (cmd->flags & RESP_MASK)
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{
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case RESP_NONE:
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sdxc_cmd.resp_type = sdxc_dev_resp_none;
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break;
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case RESP_R1:
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sdxc_cmd.resp_type = sdxc_dev_resp_r1;
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break;
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case RESP_R1B:
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sdxc_cmd.resp_type = sdxc_dev_resp_r1b;
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break;
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case RESP_R2:
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sdxc_cmd.resp_type = sdxc_dev_resp_r2;
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break;
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case RESP_R3:
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sdxc_cmd.resp_type = sdxc_dev_resp_r3;
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break;
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case RESP_R4:
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sdxc_cmd.resp_type = sdxc_dev_resp_r4;
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break;
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case RESP_R6:
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sdxc_cmd.resp_type = sdxc_dev_resp_r6;
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break;
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case RESP_R7:
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sdxc_cmd.resp_type = sdxc_dev_resp_r7;
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break;
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case RESP_R5:
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sdxc_cmd.resp_type = sdxc_dev_resp_r5;
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break;
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default:
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RT_ASSERT(NULL);
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break;
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}
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sdxc_cmd.cmd_flags = 0UL;
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xfer.command = &sdxc_cmd;
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if (data != NULL)
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{
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sdxc_data.enable_auto_cmd12 = false;
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sdxc_data.enable_auto_cmd23 = false;
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sdxc_data.enable_ignore_error = false;
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sdxc_data.data_type = sdxc_xfer_data_normal;
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sdxc_data.block_size = data->blksize;
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sdxc_data.block_cnt = data->blks;
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/* configure adma2 */
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adma_config.dma_type = sdxc_dmasel_adma2;
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adma_config.adma_table = (uint32_t*) core_local_mem_to_sys_address(BOARD_RUNNING_CORE,
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(uint32_t) mmcsd->sdxc_adma2_table);
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adma_config.adma_table_words = SDXC_ADMA_TABLE_WORDS;
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if ((req->data->flags & DATA_DIR_WRITE) != 0U)
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{
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uint32_t write_size = data->blks * data->blksize;
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if (!SDXC_IS_CACHELINE_ALIGNED(data->buf) || !SDXC_IS_CACHELINE_ALIGNED(write_size))
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{
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write_size = SDXC_CACHELINE_ALIGN_UP(write_size);
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aligned_buf = (uint32_t *) rt_malloc_align(write_size, CACHE_LINESIZE);
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memcpy(aligned_buf, data->buf, write_size);
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sdxc_data.tx_data = aligned_buf;
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rt_enter_critical();
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l1c_dc_flush((uint32_t) sdxc_data.tx_data, write_size);
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rt_exit_critical();
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}
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else
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{
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sdxc_data.tx_data = (uint32_t const *) core_local_mem_to_sys_address(BOARD_RUNNING_CORE,
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(uint32_t) data->buf);
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rt_enter_critical();
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l1c_dc_flush((uint32_t) data->buf, write_size);
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rt_exit_critical();
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}
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sdxc_data.rx_data = NULL;
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}
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else
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{
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uint32_t read_size = data->blks * data->blksize;
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if (!SDXC_IS_CACHELINE_ALIGNED(data->buf) || !SDXC_IS_CACHELINE_ALIGNED(read_size))
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{
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uint32_t aligned_read_size = SDXC_CACHELINE_ALIGN_UP(read_size);
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aligned_buf = (uint32_t *) rt_malloc_align(aligned_read_size, CACHE_LINESIZE);
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sdxc_data.rx_data = aligned_buf;
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}
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else
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{
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sdxc_data.rx_data = (uint32_t*) core_local_mem_to_sys_address(BOARD_RUNNING_CORE, (uint32_t) data->buf);
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}
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sdxc_data.tx_data = NULL;
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}
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xfer.data = &sdxc_data;
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}
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else
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{
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xfer.data = NULL;
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}
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if ((req->data->blks > 1) && ((cmd->cmd_code == READ_MULTIPLE_BLOCK) || ((cmd->cmd_code == WRITE_MULTIPLE_BLOCK))))
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{
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xfer.data->enable_auto_cmd12 = true;
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}
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err = sdxc_transfer_blocking(mmcsd->sdxc_base, &adma_config, &xfer);
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LOG_I("cmd=%d, arg=%x\n", cmd->cmd_code, cmd->arg);
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if (err != status_success)
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{
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hpm_sdmmc_host_recovery(mmcsd->sdxc_base);
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LOG_E(" ***sdxc_transfer_blocking error: %d*** -->\n", err);
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cmd->err = -RT_ERROR;
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}
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else
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{
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LOG_I(" ***sdxc_transfer_blocking passed: %d*** -->\n", err);
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if (sdxc_cmd.resp_type == sdxc_dev_resp_r2)
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{
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LOG_I("resp:0x%08x 0x%08x 0x%08x 0x%08x\n", sdxc_cmd.response[0],
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sdxc_cmd.response[1], sdxc_cmd.response[2], sdxc_cmd.response[3]);
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}
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else
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{
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LOG_I("resp:0x%08x\n", sdxc_cmd.response[0]);
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}
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}
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if ((sdxc_data.rx_data != NULL) && (cmd->err == RT_EOK))
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{
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uint32_t read_size = data->blks * data->blksize;
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if (aligned_buf != NULL)
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{
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uint32_t aligned_read_size = SDXC_CACHELINE_ALIGN_UP(read_size);
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rt_enter_critical();
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l1c_dc_invalidate((uint32_t) aligned_buf, aligned_read_size);
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rt_exit_critical();
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memcpy(data->buf, aligned_buf, read_size);
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}
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else
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{
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rt_enter_critical();
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l1c_dc_invalidate((uint32_t) data->buf, read_size);
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rt_exit_critical();
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}
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}
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if (aligned_buf != NULL)
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{
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rt_free_align(aligned_buf);
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aligned_buf = NULL;
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}
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if ((cmd->flags & RESP_MASK) == RESP_R2)
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{
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cmd->resp[3] = sdxc_cmd.response[0];
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cmd->resp[2] = sdxc_cmd.response[1];
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cmd->resp[1] = sdxc_cmd.response[2];
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cmd->resp[0] = sdxc_cmd.response[3];
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}
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else
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{
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cmd->resp[0] = sdxc_cmd.response[0];
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}
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mmcsd_req_complete(host);
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}
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/**
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* !@brief Set IO Configuration for HPMicro IO and SDXC Host
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*/
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static void hpm_sdmmc_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg)
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{
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struct hpm_mmcsd *mmcsd;
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uint32_t sdxc_clk;
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uint32_t vdd;
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RT_ASSERT(host != RT_NULL);RT_ASSERT(host->private_data != RT_NULL);RT_ASSERT(io_cfg != RT_NULL);
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mmcsd = (struct hpm_mmcsd *) host->private_data;
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vdd = io_cfg->vdd;
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static bool has_init = false;
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init_sdxc_pins(mmcsd->sdxc_base, false);
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uint32_t sdxc_clock = io_cfg->clock;
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if (sdxc_clock != 0U)
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{
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switch (io_cfg->bus_width)
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{
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case MMCSD_BUS_WIDTH_4:
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sdxc_set_data_bus_width(mmcsd->sdxc_base, sdxc_bus_width_4bit);
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break;
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case MMCSD_BUS_WIDTH_8:
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sdxc_set_data_bus_width(mmcsd->sdxc_base, sdxc_bus_width_8bit);
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break;
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default:
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sdxc_set_data_bus_width(mmcsd->sdxc_base, sdxc_bus_width_1bit);
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break;
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}
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board_sd_configure_clock(mmcsd->sdxc_base, sdxc_clk);
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}
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rt_thread_mdelay(5);
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}
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static void hpm_sdmmc_enable_sdio_irq(struct rt_mmcsd_host *host, rt_int32_t en)
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{
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RT_ASSERT(host != RT_NULL);RT_ASSERT(host->private_data != RT_NULL);
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struct hpm_mmcsd *mmcsd = (struct hpm_mmcsd *) host->private_data;
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if (en != 0)
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{
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intc_m_enable_irq_with_priority(mmcsd->irq_num, 1);
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}
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else
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{
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intc_m_disable_irq(mmcsd->irq_num);
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}
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}
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static void hpm_sdmmc_host_recovery(SDXC_Type *base)
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{
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uint32_t pstate = sdxc_get_present_status(base);
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bool need_reset_cmd_line = false;
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bool need_reset_data_line = false;
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if ((pstate & SDXC_PSTATE_CMD_INHIBIT_MASK) != 0U)
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{
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/* Reset command line */
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need_reset_cmd_line = true;
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|||
|
|
}
|
|||
|
|
|
|||
|
|
if ((pstate & SDXC_PSTATE_DAT_INHIBIT_MASK) != 0U)
|
|||
|
|
{
|
|||
|
|
/* Reset data line */
|
|||
|
|
need_reset_data_line = true;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
uint32_t int_stat = sdxc_get_interrupt_status(base);
|
|||
|
|
|
|||
|
|
if ((int_stat & 0xF0000UL) != 0U)
|
|||
|
|
{
|
|||
|
|
need_reset_cmd_line = true;
|
|||
|
|
}
|
|||
|
|
if ((int_stat & 0x700000) != 0U)
|
|||
|
|
{
|
|||
|
|
need_reset_data_line = true;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
if (need_reset_cmd_line)
|
|||
|
|
{
|
|||
|
|
sdxc_reset(base, sdxc_reset_cmd_line, 0xFFFFUL);
|
|||
|
|
}
|
|||
|
|
if (need_reset_data_line)
|
|||
|
|
{
|
|||
|
|
sdxc_reset(base, sdxc_reset_data_line, 0xFFFFUL);
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
if (need_reset_cmd_line || need_reset_data_line)
|
|||
|
|
{
|
|||
|
|
sdxc_clear_interrupt_status(base, ~0UL);
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
rt_thread_mdelay(10);
|
|||
|
|
LOG_E("%s\n", __func__);
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
int rt_hw_sdio_init(void)
|
|||
|
|
{
|
|||
|
|
rt_err_t err = RT_EOK;
|
|||
|
|
|
|||
|
|
struct rt_mmcsd_host *host = NULL;
|
|||
|
|
struct hpm_mmcsd *mmcsd = NULL;
|
|||
|
|
do
|
|||
|
|
{
|
|||
|
|
host = mmcsd_alloc_host();
|
|||
|
|
if (host == NULL)
|
|||
|
|
{
|
|||
|
|
err = -RT_ERROR;
|
|||
|
|
break;
|
|||
|
|
}
|
|||
|
|
mmcsd = rt_malloc(sizeof(struct hpm_mmcsd));
|
|||
|
|
if (mmcsd == NULL)
|
|||
|
|
{
|
|||
|
|
LOG_E("allocate hpm_mmcsd failed\n");
|
|||
|
|
err = -RT_ERROR;
|
|||
|
|
break;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
rt_memset(mmcsd, 0, sizeof(struct hpm_mmcsd));
|
|||
|
|
mmcsd->sdxc_base = BOARD_APP_SDCARD_SDXC_BASE;
|
|||
|
|
mmcsd->sdxc_adma2_table = s_sdxc_adma2_table;
|
|||
|
|
|
|||
|
|
host->ops = &hpm_mmcsd_host_ops;
|
|||
|
|
host->freq_min = 375000;
|
|||
|
|
host->freq_max = 50000000;
|
|||
|
|
host->valid_ocr = VDD_30_31 | VDD_31_32 | VDD_32_33 | VDD_33_34;
|
|||
|
|
host->flags = MMCSD_MUTBLKWRITE | MMCSD_BUSWIDTH_4 | MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ;
|
|||
|
|
|
|||
|
|
host->max_seg_size = 65535;
|
|||
|
|
host->max_dma_segs = 2;
|
|||
|
|
host->max_blk_size = 512;
|
|||
|
|
host->max_blk_count = 4096;
|
|||
|
|
|
|||
|
|
mmcsd->host = host;
|
|||
|
|
|
|||
|
|
/* Perform necessary initialization */
|
|||
|
|
board_sd_configure_clock(mmcsd->sdxc_base, 375000);
|
|||
|
|
|
|||
|
|
sdxc_config_t sdxc_config = { 0 };
|
|||
|
|
sdxc_config.data_timeout = SDXC_DATA_TIMEOUT;
|
|||
|
|
sdxc_init(mmcsd->sdxc_base, &sdxc_config);
|
|||
|
|
|
|||
|
|
host->private_data = mmcsd;
|
|||
|
|
|
|||
|
|
mmcsd_change(host);
|
|||
|
|
|
|||
|
|
} while (false);
|
|||
|
|
|
|||
|
|
if (err != RT_EOK)
|
|||
|
|
{
|
|||
|
|
if (host != NULL)
|
|||
|
|
{
|
|||
|
|
mmcsd_free_host(host);
|
|||
|
|
host = NULL;
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
return err;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
INIT_DEVICE_EXPORT(rt_hw_sdio_init);
|
|||
|
|
#endif
|