412 lines
12 KiB
C
412 lines
12 KiB
C
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/******************************************************************************
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* @file cachel1_armv7.h
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* @brief CMSIS Level 1 Cache API for Armv7-M and later
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* @version V1.0.0
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* @date 03. March 2020
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******************************************************************************/
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/*
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* Copyright (c) 2020 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#if defined ( __ICCARM__ )
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#pragma system_include /* treat file as system include file for MISRA check */
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#elif defined (__clang__)
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#pragma clang system_header /* treat file as system include file */
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#endif
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#ifndef ARM_CACHEL1_ARMV7_H
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#define ARM_CACHEL1_ARMV7_H
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/**
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\ingroup CMSIS_Core_FunctionInterface
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\defgroup CMSIS_Core_CacheFunctions Cache Functions
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\brief Functions that configure Instruction and Data cache.
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@{
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*/
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/* Cache Size ID Register Macros */
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#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
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#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
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#ifndef __SCB_DCACHE_LINE_SIZE
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#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
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#endif
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#ifndef __SCB_ICACHE_LINE_SIZE
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#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
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#endif
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/**
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\brief Enable I-Cache
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\details Turns on I-Cache
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*/
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__STATIC_FORCEINLINE void SCB_EnableICache (void)
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{
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#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
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if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */
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__DSB();
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__ISB();
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SCB->ICIALLU = 0UL; /* invalidate I-Cache */
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__DSB();
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__ISB();
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SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
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__DSB();
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__ISB();
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#endif
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}
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/**
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\brief Disable I-Cache
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\details Turns off I-Cache
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*/
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__STATIC_FORCEINLINE void SCB_DisableICache (void)
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{
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#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
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__DSB();
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__ISB();
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SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
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SCB->ICIALLU = 0UL; /* invalidate I-Cache */
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__DSB();
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__ISB();
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#endif
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}
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/**
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\brief Invalidate I-Cache
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\details Invalidates I-Cache
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*/
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__STATIC_FORCEINLINE void SCB_InvalidateICache (void)
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{
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#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
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__DSB();
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__ISB();
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SCB->ICIALLU = 0UL;
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__DSB();
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__ISB();
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#endif
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}
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/**
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\brief I-Cache Invalidate by address
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\details Invalidates I-Cache for the given address.
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I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
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I-Cache memory blocks which are part of given address + given size are invalidated.
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\param[in] addr address
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\param[in] isize size of memory block (in number of bytes)
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*/
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__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize)
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{
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#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
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if ( isize > 0 ) {
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int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U));
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uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */;
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__DSB();
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do {
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SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
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op_addr += __SCB_ICACHE_LINE_SIZE;
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op_size -= __SCB_ICACHE_LINE_SIZE;
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} while ( op_size > 0 );
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__DSB();
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__ISB();
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}
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#endif
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}
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/**
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\brief Enable D-Cache
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\details Turns on D-Cache
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*/
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__STATIC_FORCEINLINE void SCB_EnableDCache (void)
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{
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#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
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uint32_t ccsidr;
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uint32_t sets;
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uint32_t ways;
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if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */
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SCB->CSSELR = 0U; /* select Level 1 data cache */
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__DSB();
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ccsidr = SCB->CCSIDR;
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/* invalidate D-Cache */
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sets = (uint32_t)(CCSIDR_SETS(ccsidr));
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do {
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ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
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do {
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SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
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((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
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#if defined ( __CC_ARM )
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__schedule_barrier();
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#endif
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} while (ways-- != 0U);
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} while(sets-- != 0U);
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__DSB();
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SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
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__DSB();
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__ISB();
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#endif
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}
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/**
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\brief Disable D-Cache
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\details Turns off D-Cache
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*/
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__STATIC_FORCEINLINE void SCB_DisableDCache (void)
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{
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#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
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uint32_t ccsidr;
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uint32_t sets;
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uint32_t ways;
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SCB->CSSELR = 0U; /* select Level 1 data cache */
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__DSB();
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SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
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__DSB();
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ccsidr = SCB->CCSIDR;
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/* clean & invalidate D-Cache */
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sets = (uint32_t)(CCSIDR_SETS(ccsidr));
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do {
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ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
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do {
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SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
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((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
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#if defined ( __CC_ARM )
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__schedule_barrier();
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#endif
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} while (ways-- != 0U);
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} while(sets-- != 0U);
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__DSB();
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__ISB();
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#endif
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}
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/**
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\brief Invalidate D-Cache
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\details Invalidates D-Cache
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*/
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__STATIC_FORCEINLINE void SCB_InvalidateDCache (void)
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{
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#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
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uint32_t ccsidr;
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uint32_t sets;
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uint32_t ways;
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SCB->CSSELR = 0U; /* select Level 1 data cache */
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__DSB();
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ccsidr = SCB->CCSIDR;
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/* invalidate D-Cache */
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sets = (uint32_t)(CCSIDR_SETS(ccsidr));
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do {
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ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
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do {
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SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
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((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
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#if defined ( __CC_ARM )
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__schedule_barrier();
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#endif
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} while (ways-- != 0U);
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} while(sets-- != 0U);
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__DSB();
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__ISB();
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#endif
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}
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/**
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\brief Clean D-Cache
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\details Cleans D-Cache
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*/
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__STATIC_FORCEINLINE void SCB_CleanDCache (void)
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{
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#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
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uint32_t ccsidr;
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uint32_t sets;
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uint32_t ways;
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SCB->CSSELR = 0U; /* select Level 1 data cache */
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__DSB();
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ccsidr = SCB->CCSIDR;
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/* clean D-Cache */
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sets = (uint32_t)(CCSIDR_SETS(ccsidr));
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do {
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ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
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do {
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SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
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((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
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#if defined ( __CC_ARM )
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__schedule_barrier();
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#endif
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} while (ways-- != 0U);
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} while(sets-- != 0U);
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__DSB();
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__ISB();
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#endif
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}
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/**
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\brief Clean & Invalidate D-Cache
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\details Cleans and Invalidates D-Cache
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*/
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__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)
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{
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#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
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uint32_t ccsidr;
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uint32_t sets;
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uint32_t ways;
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SCB->CSSELR = 0U; /* select Level 1 data cache */
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__DSB();
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ccsidr = SCB->CCSIDR;
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/* clean & invalidate D-Cache */
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sets = (uint32_t)(CCSIDR_SETS(ccsidr));
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do {
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ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
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do {
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SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
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((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
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#if defined ( __CC_ARM )
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__schedule_barrier();
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#endif
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} while (ways-- != 0U);
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} while(sets-- != 0U);
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__DSB();
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__ISB();
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#endif
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}
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/**
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\brief D-Cache Invalidate by address
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\details Invalidates D-Cache for the given address.
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D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
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D-Cache memory blocks which are part of given address + given size are invalidated.
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\param[in] addr address
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\param[in] dsize size of memory block (in number of bytes)
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*/
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__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize)
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{
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#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
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if ( dsize > 0 ) {
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int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
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uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
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__DSB();
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do {
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SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
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op_addr += __SCB_DCACHE_LINE_SIZE;
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op_size -= __SCB_DCACHE_LINE_SIZE;
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} while ( op_size > 0 );
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__DSB();
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__ISB();
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}
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#endif
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}
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/**
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\brief D-Cache Clean by address
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\details Cleans D-Cache for the given address
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D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity.
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D-Cache memory blocks which are part of given address + given size are cleaned.
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\param[in] addr address
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\param[in] dsize size of memory block (in number of bytes)
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*/
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__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
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{
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#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
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if ( dsize > 0 ) {
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int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
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uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
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__DSB();
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||
|
|
|
||
|
|
do {
|
||
|
|
SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
|
||
|
|
op_addr += __SCB_DCACHE_LINE_SIZE;
|
||
|
|
op_size -= __SCB_DCACHE_LINE_SIZE;
|
||
|
|
} while ( op_size > 0 );
|
||
|
|
|
||
|
|
__DSB();
|
||
|
|
__ISB();
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
/**
|
||
|
|
\brief D-Cache Clean and Invalidate by address
|
||
|
|
\details Cleans and invalidates D_Cache for the given address
|
||
|
|
D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity.
|
||
|
|
D-Cache memory blocks which are part of given address + given size are cleaned and invalidated.
|
||
|
|
\param[in] addr address (aligned to 32-byte boundary)
|
||
|
|
\param[in] dsize size of memory block (in number of bytes)
|
||
|
|
*/
|
||
|
|
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
|
||
|
|
{
|
||
|
|
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||
|
|
if ( dsize > 0 ) {
|
||
|
|
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
|
||
|
|
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
|
||
|
|
|
||
|
|
__DSB();
|
||
|
|
|
||
|
|
do {
|
||
|
|
SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
|
||
|
|
op_addr += __SCB_DCACHE_LINE_SIZE;
|
||
|
|
op_size -= __SCB_DCACHE_LINE_SIZE;
|
||
|
|
} while ( op_size > 0 );
|
||
|
|
|
||
|
|
__DSB();
|
||
|
|
__ISB();
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
/*@} end of CMSIS_Core_CacheFunctions */
|
||
|
|
|
||
|
|
#endif /* ARM_CACHEL1_ARMV7_H */
|