241 lines
9.3 KiB
C
241 lines
9.3 KiB
C
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/*
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* Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
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* Copyright 2016 - 2017 NXP
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <usb/include/usb.h>
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#include "fsl_device_registers.h"
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#include <usb/phy/usb_phy.h>
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void *USB_EhciPhyGetBase(uint8_t controllerId)
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{
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void *usbPhyBase = NULL;
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#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U))
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uint32_t instance;
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uint32_t newinstance = 0;
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uint32_t usbphy_base_temp[] = USBPHY_BASE_ADDRS;
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uint32_t usbphy_base[] = USBPHY_BASE_ADDRS;
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if (controllerId < kUSB_ControllerEhci0)
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{
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return NULL;
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}
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controllerId = controllerId - kUSB_ControllerEhci0;
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for (instance = 0; instance < (sizeof(usbphy_base_temp) / sizeof(usbphy_base_temp[0])); instance++)
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{
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if (usbphy_base_temp[instance])
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{
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usbphy_base[newinstance++] = usbphy_base_temp[instance];
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}
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}
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if (controllerId > newinstance)
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{
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return NULL;
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}
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usbPhyBase = (void *)usbphy_base[controllerId];
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#endif
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return usbPhyBase;
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}
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/*!
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* @brief ehci phy initialization.
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*
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* This function initialize ehci phy IP.
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*
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* @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t.
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* @param[in] freq the external input clock.
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* for example: if the external input clock is 16M, the parameter freq should be 16000000.
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*
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* @retval kStatus_USB_Success cancel successfully.
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* @retval kStatus_USB_Error the freq value is incorrect.
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*/
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uint32_t USB_EhciPhyInit(uint8_t controllerId, uint32_t freq, usb_phy_config_struct_t *phyConfig)
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{
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#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U))
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USBPHY_Type *usbPhyBase;
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usbPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId);
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if (NULL == usbPhyBase)
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{
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return kStatus_USB_Error;
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}
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#if ((defined FSL_FEATURE_SOC_ANATOP_COUNT) && (FSL_FEATURE_SOC_ANATOP_COUNT > 0U))
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ANATOP->HW_ANADIG_REG_3P0.RW =
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(ANATOP->HW_ANADIG_REG_3P0.RW &
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(~(ANATOP_HW_ANADIG_REG_3P0_OUTPUT_TRG(0x1F) | ANATOP_HW_ANADIG_REG_3P0_ENABLE_ILIMIT_MASK))) |
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ANATOP_HW_ANADIG_REG_3P0_OUTPUT_TRG(0x17) | ANATOP_HW_ANADIG_REG_3P0_ENABLE_LINREG_MASK;
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ANATOP->HW_ANADIG_USB2_CHRG_DETECT.SET =
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ANATOP_HW_ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B_MASK | ANATOP_HW_ANADIG_USB2_CHRG_DETECT_EN_B_MASK;
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#endif
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#if (defined USB_ANALOG)
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USB_ANALOG->INSTANCE[controllerId - kUSB_ControllerEhci0].CHRG_DETECT_SET = USB_ANALOG_CHRG_DETECT_CHK_CHRG_B(1) | USB_ANALOG_CHRG_DETECT_EN_B(1);
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#endif
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#if ((!(defined FSL_FEATURE_SOC_CCM_ANALOG_COUNT)) && (!(defined FSL_FEATURE_SOC_ANATOP_COUNT)))
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usbPhyBase->TRIM_OVERRIDE_EN = 0x001fU; /* override IFR value */
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#endif
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usbPhyBase->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK; /* support LS device. */
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usbPhyBase->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL3_MASK; /* support external FS Hub with LS device connected. */
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/* PWD register provides overall control of the PHY power state */
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usbPhyBase->PWD = 0U;
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/* Decode to trim the nominal 17.78mA current source for the High Speed TX drivers on USB_DP and USB_DM. */
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usbPhyBase->TX =
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((usbPhyBase->TX & (~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK))) |
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(USBPHY_TX_D_CAL(phyConfig->D_CAL) | USBPHY_TX_TXCAL45DP(phyConfig->TXCAL45DP) |
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USBPHY_TX_TXCAL45DM(phyConfig->TXCAL45DM)));
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#endif
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return kStatus_USB_Success;
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}
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/*!
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* @brief ehci phy initialization for suspend and resume.
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*
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* This function initialize ehci phy IP for suspend and resume.
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*
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* @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t.
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* @param[in] freq the external input clock.
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* for example: if the external input clock is 16M, the parameter freq should be 16000000.
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*
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* @retval kStatus_USB_Success cancel successfully.
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* @retval kStatus_USB_Error the freq value is incorrect.
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*/
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uint32_t USB_EhciLowPowerPhyInit(uint8_t controllerId, uint32_t freq, usb_phy_config_struct_t *phyConfig)
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{
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#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U))
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USBPHY_Type *usbPhyBase;
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usbPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId);
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if (NULL == usbPhyBase)
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{
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return kStatus_USB_Error;
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}
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#if ((!(defined FSL_FEATURE_SOC_CCM_ANALOG_COUNT)) && (!(defined FSL_FEATURE_SOC_ANATOP_COUNT)))
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usbPhyBase->TRIM_OVERRIDE_EN = 0x001fU; /* override IFR value */
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#endif
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#if ((defined USBPHY_CTRL_AUTORESUME_EN_MASK) && (USBPHY_CTRL_AUTORESUME_EN_MASK > 0U))
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usbPhyBase->CTRL |= USBPHY_CTRL_AUTORESUME_EN_MASK;
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#else
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usbPhyBase->CTRL |= USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK;
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#endif
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usbPhyBase->CTRL |= USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK | USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK;
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usbPhyBase->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK; /* support LS device. */
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usbPhyBase->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL3_MASK; /* support external FS Hub with LS device connected. */
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/* PWD register provides overall control of the PHY power state */
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usbPhyBase->PWD = 0U;
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#if ((!(defined FSL_FEATURE_SOC_CCM_ANALOG_COUNT)) && (!(defined FSL_FEATURE_SOC_ANATOP_COUNT)))
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/* now the 480MHz USB clock is up, then configure fractional divider after PLL with PFD
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* pfd clock = 480MHz*18/N, where N=18~35
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* Please note that USB1PFDCLK has to be less than 180MHz for RUN or HSRUN mode
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*/
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usbPhyBase->ANACTRL |= USBPHY_ANACTRL_PFD_FRAC(24); /* N=24 */
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usbPhyBase->ANACTRL |= USBPHY_ANACTRL_PFD_CLK_SEL(1); /* div by 4 */
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usbPhyBase->ANACTRL &= ~USBPHY_ANACTRL_DEV_PULLDOWN_MASK;
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usbPhyBase->ANACTRL &= ~USBPHY_ANACTRL_PFD_CLKGATE_MASK;
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while (!(usbPhyBase->ANACTRL & USBPHY_ANACTRL_PFD_STABLE_MASK))
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{
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}
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#endif
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/* Decode to trim the nominal 17.78mA current source for the High Speed TX drivers on USB_DP and USB_DM. */
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usbPhyBase->TX =
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((usbPhyBase->TX & (~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK))) |
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(USBPHY_TX_D_CAL(phyConfig->D_CAL) | USBPHY_TX_TXCAL45DP(phyConfig->TXCAL45DP) |
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USBPHY_TX_TXCAL45DM(phyConfig->TXCAL45DM)));
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#endif
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return kStatus_USB_Success;
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}
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/*!
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* @brief ehci phy de-initialization.
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*
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* This function de-initialize ehci phy IP.
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*
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* @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t.
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*/
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void USB_EhciPhyDeinit(uint8_t controllerId)
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{
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#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U))
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USBPHY_Type *usbPhyBase;
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usbPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId);
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if (NULL == usbPhyBase)
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{
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return;
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}
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#if ((!(defined FSL_FEATURE_SOC_CCM_ANALOG_COUNT)) && (!(defined FSL_FEATURE_SOC_ANATOP_COUNT)))
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usbPhyBase->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_POWER_MASK; /* power down PLL */
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usbPhyBase->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK; /* disable USB clock output from USB PHY PLL */
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#endif
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usbPhyBase->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* set to 1U to gate clocks */
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#endif
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}
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/*!
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* @brief ehci phy disconnect detection enable or disable.
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*
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* This function enable/disable host ehci disconnect detection.
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*
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* @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t.
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* @param[in] enable
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* 1U - enable;
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* 0U - disable;
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*/
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void USB_EhcihostPhyDisconnectDetectCmd(uint8_t controllerId, uint8_t enable)
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{
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#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U))
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USBPHY_Type *usbPhyBase;
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usbPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId);
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if (NULL == usbPhyBase)
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{
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return;
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}
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if (enable)
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{
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usbPhyBase->CTRL |= USBPHY_CTRL_ENHOSTDISCONDETECT_MASK;
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}
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else
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{
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usbPhyBase->CTRL &= (~USBPHY_CTRL_ENHOSTDISCONDETECT_MASK);
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}
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#endif
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}
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