94 lines
4.7 KiB
C
94 lines
4.7 KiB
C
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/*!
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\file gd32f3x0_wwdgt.h
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\brief definitions for the WWDGT
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\version 2017-06-06, V1.0.0, firmware for GD32F3x0
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\version 2019-06-01, V2.0.0, firmware for GD32F3x0
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*/
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/*
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Copyright (c) 2019, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#ifndef GD32F3X0_WWDGT_H
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#define GD32F3X0_WWDGT_H
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#include "gd32f3x0.h"
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/* WWDGT definitions */
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#define WWDGT WWDGT_BASE
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/* registers definitions */
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#define WWDGT_CTL REG32(WWDGT + 0x00000000U) /*!< WWDGT control register */
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#define WWDGT_CFG REG32(WWDGT + 0x00000004U) /*!< WWDGT configuration register */
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#define WWDGT_STAT REG32(WWDGT + 0x00000008U) /*!< WWDGT status register */
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/* bits definitions */
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/* WWDGT_CTL */
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#define WWDGT_CTL_CNT BITS(0,6) /*!< WWDGT counter value */
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#define WWDGT_CTL_WDGTEN BIT(7) /*!< WWDGT counter enable */
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/* WWDGT_CFG */
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#define WWDGT_CFG_WIN BITS(0,6) /*!< WWDGT counter window value */
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#define WWDGT_CFG_PSC BITS(7,8) /*!< WWDGT prescaler divider value */
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#define WWDGT_CFG_EWIE BIT(9) /*!< WWDGT early wakeup interrupt enable */
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/* WWDGT_STAT */
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#define WWDGT_STAT_EWIF BIT(0) /*!< WWDGT early wakeup interrupt flag */
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/* constants definitions */
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/* WWDGT_CTL register value */
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#define CTL_CNT(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U)) /*!< write value to WWDGT_CTL_CNT bit field */
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/* WWDGT_CFG register value */
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#define CFG_WIN(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U)) /*!< write value to WWDGT_CFG_WIN bit field */
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#define CFG_PSC(regval) (BITS(7,8) & ((uint32_t)(regval) << 7U)) /*!< write value to WWDGT_CFG_PSC bit field */
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#define WWDGT_CFG_PSC_DIV1 ((uint32_t)CFG_PSC(0)) /*!< the time base of WWDGT = (PCLK1/4096)/1 */
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#define WWDGT_CFG_PSC_DIV2 ((uint32_t)CFG_PSC(1)) /*!< the time base of WWDGT = (PCLK1/4096)/2 */
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#define WWDGT_CFG_PSC_DIV4 ((uint32_t)CFG_PSC(2)) /*!< the time base of WWDGT = (PCLK1/4096)/4 */
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#define WWDGT_CFG_PSC_DIV8 ((uint32_t)CFG_PSC(3)) /*!< the time base of WWDGT = (PCLK1/4096)/8 */
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/* function declarations */
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/* reset the window watchdog timer configuration */
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void wwdgt_deinit(void);
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/* start the window watchdog timer counter */
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void wwdgt_enable(void);
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/* configure the window watchdog timer counter value */
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void wwdgt_counter_update(uint16_t counter_value);
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/* configure counter value, window value, and prescaler divider value */
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void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler);
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/* enable early wakeup interrupt of WWDGT */
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void wwdgt_interrupt_enable(void);
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/* check early wakeup interrupt state of WWDGT */
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FlagStatus wwdgt_flag_get(void);
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/* clear early wakeup interrupt state of WWDGT */
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void wwdgt_flag_clear(void);
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#endif /* GD32F3X0_WWDGT_H */
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