269 lines
6.3 KiB
C
269 lines
6.3 KiB
C
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/*
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* Copyright (c) 2023 HPMicro
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#include <rthw.h>
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#include <rtdevice.h>
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#include <rtdbg.h>
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#include "board.h"
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#include "drv_ewdt.h"
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#include "hpm_ewdg_drv.h"
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#include "hpm_sysctl_drv.h"
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#ifdef BSP_USING_EWDG
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#define EWDG_CNT_CLK_FREQ 32768UL
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typedef struct hpm_wdog
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{
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EWDG_Type *wdog_base;
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char *device_name;
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clock_name_t clock_name;
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uint32_t irq_num;
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rt_watchdog_t *wdog;
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}hpm_wdog_t;
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static rt_err_t hpm_wdog_init(rt_watchdog_t *wdt);
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static rt_err_t hpm_wdog_open(rt_watchdog_t *wdt, rt_uint16_t oflag);
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static rt_err_t hpm_wdog_close(rt_watchdog_t *wdt);
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static rt_err_t hpm_wdog_refresh(rt_watchdog_t *wdt);
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static rt_err_t hpm_wdog_control(rt_watchdog_t *wdt, int cmd, void *args);
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static void hpm_wdog_isr(rt_watchdog_t *wdt);
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#if defined(BSP_USING_EWDG0)
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rt_watchdog_t wdog0;
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void wdog0_isr(void)
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{
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hpm_wdog_isr(&wdog0);
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}
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SDK_DECLARE_EXT_ISR_M(IRQn_EWDG0, wdog0_isr)
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#endif
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#if defined(BSP_USING_EWDG1)
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rt_watchdog_t wdog1;
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void wdog1_isr(void)
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{
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hpm_wdog_isr(&wdog1);
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}
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SDK_DECLARE_EXT_ISR_M(IRQn_EWDG1, wdog1_isr)
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#endif
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#if defined(BSP_USING_EWDG2)
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rt_watchdog_t wdog2;
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void wdog2_isr(void)
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{
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hpm_wdog_isr(&wdog2);
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}
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SDK_DECLARE_EXT_ISR_M(IRQn_EWDG2, wdog2_isr)
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#endif
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#if defined(BSP_USING_EWDG3)
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rt_watchdog_t wdog3;
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void wdog3_isr(void)
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{
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hpm_wdog_isr(&wdog3);
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}
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SDK_DECLARE_EXT_ISR_M(IRQn_EWDG3, wdog3_isr)
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#endif
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static hpm_wdog_t wdogs[] = {
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#ifdef BSP_USING_EWDG0
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{
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.wdog_base = HPM_EWDG0,
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.device_name = "wdt0",
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.clock_name = clock_watchdog0,
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.irq_num = IRQn_EWDG0,
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.wdog = &wdog0,
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},
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#endif
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#ifdef BSP_USING_EWDG1
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{
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.wdog_base = HPM_EWDG1,
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.device_name = "wdt1",
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.clock_name = clock_watchdog1,
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.irq_num = IRQn_EWDG1,
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.wdog = &wdog1,
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},
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#endif
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#ifdef BSP_USING_EWDG2
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{
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.wdog_base = HPM_EWDG2,
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.device_name = "wdt2",
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.clock_name = clock_watchdog2,
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.irq_num = IRQn_EWDG2,
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.wdog = &wdog2,
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},
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#endif
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#ifdef BSP_USING_EWDG3
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{
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.wdog_name = HPM_EWDG3,
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.device_name = "wdt3",
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.clock_name = clock_watchdog3,
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.irq_num = IRQn_EWDG3,
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.wdog = &wdog3,
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},
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#endif
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};
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static struct rt_watchdog_ops hpm_wdog_ops = {
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.init = hpm_wdog_init,
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.control = hpm_wdog_control,
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};
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static rt_err_t hpm_wdog_init(rt_watchdog_t *wdt)
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{
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hpm_wdog_t *hpm_wdog = (hpm_wdog_t*)wdt->parent.user_data;
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EWDG_Type *base = hpm_wdog->wdog_base;
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ewdg_config_t config;
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printf("Init Watchdog\n");
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ewdg_get_default_config(base, &config);
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/* Enable EWDG */
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config.enable_watchdog = true;
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config.ctrl_config.use_lowlevel_timeout = false;
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/* Enable EWDG Timeout Reset */
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config.int_rst_config.enable_timeout_reset = true;
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/* Set EWDG Count clock source to OSC32 */
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config.ctrl_config.cnt_clk_sel = ewdg_cnt_clk_src_ext_osc_clk;
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/* Set the EWDG reset timeout to 101ms */
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config.cnt_src_freq = EWDG_CNT_CLK_FREQ;
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config.ctrl_config.timeout_reset_us = 101UL * 1000UL;
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ewdg_init(base, &config);
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return RT_EOK;
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}
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static rt_err_t hpm_wdog_open(rt_watchdog_t *wdt, rt_uint16_t oflag)
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{
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hpm_wdog_t *hpm_wdog = (hpm_wdog_t*)wdt->parent.user_data;
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EWDG_Type *base = hpm_wdog->wdog_base;
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rt_enter_critical();
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ewdg_enable(base);
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rt_exit_critical();
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}
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static rt_err_t hpm_wdog_close(rt_watchdog_t *wdt)
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{
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hpm_wdog_t *hpm_wdog = (hpm_wdog_t*)wdt->parent.user_data;
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EWDG_Type *base = hpm_wdog->wdog_base;
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rt_enter_critical();
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ewdg_disable(base);
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rt_exit_critical();
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return RT_EOK;
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}
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static rt_err_t hpm_wdog_refresh(rt_watchdog_t *wdt)
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{
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hpm_wdog_t *hpm_wdog = (hpm_wdog_t*)wdt->parent.user_data;
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EWDG_Type *base = hpm_wdog->wdog_base;
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rt_enter_critical();
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ewdg_refresh(base);
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rt_exit_critical();
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return RT_EOK;
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}
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static rt_err_t hpm_wdog_control(rt_watchdog_t *wdt, int cmd, void *args)
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{
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rt_err_t ret = RT_EOK;
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hpm_wdog_t *hpm_wdog = (hpm_wdog_t*)wdt->parent.user_data;
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EWDG_Type *base = hpm_wdog->wdog_base;
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ewdg_config_t config;
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uint32_t temp;
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switch (cmd)
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{
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case RT_DEVICE_CTRL_WDT_SET_TIMEOUT:
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RT_ASSERT(*(uint32_t *)args != 0);
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temp = *(uint32_t *)args;
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temp *= 1000000U; /* Convert to microseconds */
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ewdg_get_default_config(base, &config);
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config.enable_watchdog = true;
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config.int_rst_config.enable_timeout_reset = true;
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config.ctrl_config.use_lowlevel_timeout = false;
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uint32_t ewdg_src_clk_freq = EWDG_CNT_CLK_FREQ;
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config.ctrl_config.cnt_clk_sel = ewdg_cnt_clk_src_ext_osc_clk;
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/* Set the EWDG reset timeout to 1 second */
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config.cnt_src_freq = ewdg_src_clk_freq;
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config.ctrl_config.timeout_reset_us = temp;
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/* Initialize the EWDG */
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hpm_stat_t status = ewdg_init(base, &config);
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if (status != status_success) {
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printf(" EWDG initialization failed, error_code=%d\n", status);
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}
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/* delay 1ms to ensure above configure take effective*/
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rt_thread_mdelay(1);
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break;
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case RT_DEVICE_CTRL_WDT_KEEPALIVE:
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hpm_wdog_refresh(wdt);
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break;
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case RT_DEVICE_CTRL_WDT_START:
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hpm_wdog_open(wdt, *(uint16_t*)args);
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break;
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case RT_DEVICE_CTRL_WDT_STOP:
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hpm_wdog_close(wdt);
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break;
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default:
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ret = RT_EINVAL;
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break;
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}
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return RT_EOK;
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}
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void hpm_wdog_isr(rt_watchdog_t *wdt)
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{
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hpm_wdog_t *hpm_wdog = (hpm_wdog_t*)wdt->parent.user_data;
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EWDG_Type *base = hpm_wdog->wdog_base;
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uint32_t ewdg_stat = ewdg_get_status_flags(base);
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if ((ewdg_stat & EWDG_INT_TIMEOUT) != 0) {
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ewdg_refresh(base);
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}
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ewdg_clear_status_flags(base, ewdg_stat);
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}
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int rt_hw_wdt_init(void)
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{
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rt_err_t err = RT_EOK;
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#if defined(BSP_USING_EWDG)
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for (uint32_t i = 0; i < sizeof(wdogs) / sizeof(wdogs[0]); i++)
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{
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wdogs[i].wdog->ops = &hpm_wdog_ops;
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clock_add_to_group(wdogs[i].clock_name, 0);
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err = rt_hw_watchdog_register(wdogs[i].wdog, wdogs[i].device_name, RT_DEVICE_FLAG_RDWR, (void *)&wdogs[i]);
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if (err != RT_EOK)
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{
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LOG_E("rt device %s failed, status=%d\n", wdogs[i].device_name, err);
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}
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}
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#endif
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return err;
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}
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INIT_BOARD_EXPORT(rt_hw_wdt_init);
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#endif /* RT_USING_WDT */
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